Datasheet

Supply, reset and clock management ST7LITE20F2 ST7LITE25F2 ST7LITE29F2
44/170 DocID8349 Rev 7
Figure 19. Using the AVD to monitor V
DD
7.6.3 Low power modes
Interrupts
The AVD interrupt event generates an interrupt if the corresponding enable control bit
(AVDIE) is set and the interrupt mask in the CC register is reset (RIM instruction).
V
DD
V
IT+(AVD)
V
IT-(AVD)
AVDF bit
01RESET
if AVDIE bit = 1
V
hyst
AVD interrupt
request
Interrupt cleared by
V
IT+(LVD)
V
IT-(LVD)
LVD RESET
Early warning interrupt
(Power has dropped, MCU not
not yet in reset)
01
hardware
Interrupt cleared by
reset
Table 9. Effect of low power modes on SI
Mode Description
WAIT No effect on SI. AVD interrupts cause the device to exit from WAIT mode.
HALT The SICSR register is frozen. The AVD remains active.
Table 10. Interrupt control bits
Interrupt event Event flag Enable control bit Exit from Wait Exit from Halt
AVD event AVDF AVDIE Yes No