Datasheet

Supply, reset and clock management ST7LITE20F2 ST7LITE25F2 ST7LITE29F2
42/170 DocID8349 Rev 7
The LVD Reset circuitry generates a reset when VDD is below:
• V
IT+(LVD)
when V
DD
is rising
• V
IT-(LVD)
when V
DD
is falling.
The LVD function is illustrated in Figure 17.
The voltage threshold can be configured by option byte to be low, medium or high.
Provided the minimum V
DD
value (guaranteed for the oscillator frequency) is above
V
IT-(LVD)
, the MCU can only be in two modes:
• under full software control
• in static safe reset.
In these conditions, secure operation is always ensured for the application without the need
for external reset hardware.
During a Low Voltage Detector Reset, the RESET
pin is held low, thus permitting the MCU
to reset other devices.
Note: The LVD allows the device to be used without any external RESET circuitry.
The LVD is an optional function which can be selected by option byte.
Use of LVD with capacitive power supply: with this type of power supply, if power cuts occur
in the application, it is recommended to pull V
DD
down to 0V to ensure optimum restart
conditions. Refer to circuit example in
Figure 84: RESET pin protection when LVD is
enabled
It is recommended to make sure that the V
DD
supply voltage rises monotonously when the
device is exiting from Reset, to ensure the application functions properly.
Figure 17. Low voltage detector vs. Reset
V
DD
V
IT+
(LVD)
RESET
V
IT-
(LVD)
V
hys