Datasheet

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ST7LITE20F2 ST7LITE25F2 ST7LITE29F2 Supply, reset and clock management
169
7.5.5 Internal watchdog RESET
The RESET sequence generated by a internal Watchdog counter overflow is shown in
Figure 16.
Starting from the Watchdog counter underflow, the device RESET
pin acts as an output that
is pulled low during at least t
w(RSTL)out
.
Figure 16. RESET sequences
7.6 System integrity management (SI)
The system integrity management block contains the low voltage detector (LVD) and
auxiliary voltage detector (AVD) functions. It is managed by the SICSR register.
Note: A reset can also be triggered following the detection of an illegal opcode or prebyte code.
Refer to
Section 12.2.1: Illegal opcode reset for further details.
7.6.1 Low voltage detector (LVD)
The low voltage detector function (LVD) generates a static reset when the V
DD
supply
voltage is below a V
IT-(LVD)
reference value. This means that it secures the power-up as well
as the power-down keeping the ST7 in reset.
The V
IT-(LVD)
reference value for a voltage drop is lower than the V
IT+(LVD)
reference value
for power-on in order to avoid a parasitic reset when the MCU starts running and sinks
current on the supply (hysteresis).
V
DD
Run
RESET PIN
External
Watchdog
Active phase
V
IT+(LVD)
V
IT-(LVD)
t
h(RSTL)in
Run
Watchdog underflow
t
w(RSTL)out
Run Run
RESET
RESET
SOURCE
External
RESET
LVD
RESET
Watchdog
RESET
Internal RESET (256 or 4096 T
CPU
)
Vector fetch
Active
phase
Active
phase