Datasheet

Supply, reset and clock management ST7LITE20F2 ST7LITE25F2 ST7LITE29F2
36/170 DocID8349 Rev 7
for TA = -40 to +85°C) @ VDD = 4.5 to 5.5 V).
Refer to Section 7.6.4: Register description for a description of the LOCKED bit in the
SICSR register.
7.3 Register description
Main clock control/status register (MCCSR)
Read / Write
Reset value: 0000 0000 (00h)
• Bits 7:2 = Reserved, must be kept cleared
• Bit 1 = MCO Main Clock Out enable
This bit is read/write by software and cleared by hardware after a reset. This bit allows
to enable the MCO output clock.
0: MCO clock disabled, I/O port free for general purpose I/O.
1: MCO clock enabled.
• Bit 0 = SMS Slow Mode select
This bit is read/write by software and cleared by hardware after a reset. This bit selects
the input clock f
OSC2
or f
OSC2
/32.
0: Normal mode (f
CPU =
f
OSC2
1: Slow mode (f
CPU =
f
OSC2
/32)
RC control register (RCCR)
Read / Write
Reset value: 1111 1111 (FFh)
• Bits 7:0 = CR[7:0] RC oscillator frequency adjustment bits
These bits must be written immediately after reset to adjust the RC oscillator frequency
and to obtain an accuracy of 1%. The application can store the correct value for each
voltage range in EEPROM and write it to this register at startup.
00h = maximum available frequency
FFh = lowest available frequency
Note: To tune the oscillator, write a serie of different values in the register until the correct
frequency is reached. The fastest method is to use a dichotomy starting with 80h.
7 0
000000MCOSMS
7 0
CR70 CR60 CR50 CR40 CR30 CR20 CR10 CR0