Datasheet

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ST7LITE20F2 ST7LITE25F2 ST7LITE29F2 Data EEPROM
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Figure 8. Data EEPROM Write operation
Note: If a programming cycle is interrupted (by a reset action), the integrity of the data in memory
is not guaranteed.
5.4 Power saving modes
WAIT mode
The DATA EEPROM can enter WAIT mode on execution of the WFI instruction of the
microcontroller or when the microcontroller enters ACTIVE-HALT mode.The DATA
EEPROM will immediately enter this mode if there is no programming in progress, otherwise
the DATA EEPROM will finish the cycle and then enter WAIT mode.
ACTIVE-HALT mode
Refer to WAIT mode.
HALT mode
The DATA EEPROM immediately enters HALT mode if the microcontroller executes the
HALT instruction. Therefore the EEPROM will stop the function in progress, and data may
be corrupted.
5.5 Access error handling
If a read access occurs while E2LAT=1, then the data bus will not be driven.
If a write access occurs while E2LAT=0, then the data on the bus will not be latched.
If a programming cycle is interrupted (by a RESET action), the memory data will not be
guaranteed.
Table 4. Row definition
⇓ Row / Byte ⇒ 0 1 2 3 ... 30 31 Physical address
0 00h...1Fh
1 20h...3Fh
...
N Nx20h...Nx20h+1Fh
Byte 1 Byte 2 Byte 32
PHASE 1
Programming cycle
Read operation impossible
PHASE 2
Read operation possible
E2LAT bit
E2PGM bit
Writing data latches Waiting E2PGM and E2LAT to fall
Set by USER application
Cleared by hardware