Datasheet
DocID8349 Rev 7 15/170
ST7LITE20F2 ST7LITE25F2 ST7LITE29F2 Pin description
169
2 Pin description
Figure 2. 20-pin SO package pinout
Figure 3. 20-pin DIP package pinout
Legend and abbreviations for device pin description (seeTable 2 below):
• Type:
– I = input
– O = output
– S = supply
• In/Output level:
–C
T
= CMOS 0.3V
DD
/0.7V
DD
with input trigger
• Output level:
– HS = 20mA high sink (on N-buffer only)
20
19
18
17
16
15
14
13
1
2
3
4
5
6
7
8
V
SS
V
DD
AIN5/PB5
CLKIN/AIN4/PB4
MOSI/AIN3/PB3
MISO/AIN2/PB2
SCK/AIN1/PB1
SS
/AIN0/PB0
OSC1/CLKIN
OSC2
PA5 (HS)/ATPWM3/ICCDATA
PA4 (HS)/ATPWM2
PA3 (HS)/ATPWM1
PA2 (HS)/ATPWM0
PA1 (HS)/ATIC
PA0 (HS)/LTIC
(HS) 20mA high sink capability
eix associated external interrupt vector
12
11
9
10
IN/AIN6/PB6
PA7(HS)
PA6/MCO/ICCCLK/BREAK
RESET
ei
3
ei2
ei
0
ei
1
20
19
18
17
16
15
14
13
1
2
3
4
5
6
7
8
MISO/AIN2/PB2
MOSI/AIN3/PB3
ATPWM2/PA4(HS)
ATPWM3/ICCDATA/PA5(HS)
MCO/ICCCLK/BREAK/PA6
PA7(HS)
AIN6/PB6
AIN5/PB5
SCK/AIN1/PB1
SS
/AIN0/PB0
PA0(HS)/LTIC
OSC2
OSC1/CLKIN
V
SS
V
DD
RESET
(HS) 20mA high sink capability
eix associated external interrupt vector
12
11
9
10
ATPWM1/PA3(HS)
PA2(HS)/ATPWM0
PA1(HS)/ATIC
CLKIN/AIN4/PB4
ei3
ei3
ei2
ei1
ei0
ei0