Datasheet

DocID8349 Rev 7 145/170
ST7LITE20F2 ST7LITE25F2 ST7LITE29F2 Electrical characteristics
169
1. Check that all recommendations related to ICCCLK and reset circuit have been applied
(see
Table 2: Device pin description)
2. Check that the power supply is properly decoupled (100nF + 10µF close to the MCU).
Refer to AN1709 and AN2017. If this cannot be done, it is recommended to put a
100nF + 1MΩ pull-down on the
RESET pin.
3. The capacitors connected on the RESET pin and also the power supply are key to
avoid any startup marginality. In most cases, steps 1 and 2 above are sufficient for a
robust solution. Otherwise: replace 10nF pull-down on the
RESET pin with a 5µF to
20µF capacitor.”
Note: Please refer to Section 12.2.1: Illegal opcode reset for more details.
13.10 Communication interface characteristics
13.10.1 Serial peripheral interface (SPI)
Subject to general operating conditions for V
DD
, f
OSC
, and T
A
unless otherwise specified.
Refer to I/O port characteristics for more details on the input/output alternate function
characteristics (SS
, SCK, MOSI, MISO).
Table 83. Serial peripheral interface (SPI)
(1)
1. Subject to general operating conditions for V
DD
, f
OSC
, and T
A
unless otherwise specified.
Symbol Parameter Conditions Min Max Unit
f
SCK =
1/t
c(SCK)
SPI clock frequency
Master
f
CPU
= 8MHz
f
CPU
/128 = 0.0625 f
CPU
/4 = 2
MHz
Slave
f
CPU
= 8MHz
0f
CPU
/2 = 4
t
r(SCK)
t
f(SCK)
SPI clock rise and fall time − see I/O port pin description
t
su(SS)
(2)
2. Data based on design simulation and/or characterization results, not tested in production.
SS setup time
(3)
Slave (4 x T
CPU
) +150 −
ns
t
h(SS)
(2)
SS hold time Slave 120 −
t
w(SCKH)
t
w(SCKL)
SCK high and low time
Master
Slave
100
90
−
t
su(MI)
t
su(SI)
Data input setup time
Master
Slave
100
100
−
t
h(MI)
t
h(SI)
Data input hold time
Master
Slave
100
100
−
t
a(SO)
Data output access time Slave 0 120
t
dis(SO)
Data output disable time Slave − 240
t
v(SO)
Data output valid time
Slave (after
enable edge)
− 120
t
h(SO)
Data output hold time 0 −
t
v(MO)
Data output valid time
Master (after
enable edge)
− 120
t
h(MO)
Data output hold time 0 −