Datasheet

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ST7LITE20F2 ST7LITE25F2 ST7LITE29F2 Electrical characteristics
169
Figure 82. Typical V
OL
vs. V
DD
(high-sink I/Os)
Figure 83. Typical V
DD
-V
OH
vs. V
DD
13.9 Control pin characteristics
0.00
0.10
0.20
0.30
0.40
0.50
0.60
0.70
2.4 3 5
VDD (V)
VOL vs VDD (HS) at lio=8mA
-45
0°C
25°C
90°C
130°C
0.00
0.10
0.20
0.30
0.40
0.50
0.60
0.70
0.80
0.90
1.00
2.4 3 5
VDD (V)
VOL vs VDD (HS) at lio=20mA
-45
0°C
25°C
90°C
130°C
0.40
0.50
0.60
0.70
0.80
0.90
1.00
1.10
2.4 2.7 3 4 5
VDD (V)
VDD-VOH (V) at lio=-2mA
-45°C
0°C
25°C
90°C
130°C
0.80
0.90
1.00
1.10
1.20
1.30
1.40
1.50
1.60
1.70
1.80
45
VDD
VDD-VOH at lio=-5mA
-45°C
0°C
25°C
90°C
130°C
Table 82. Asynchronous RESET Pin
(1)
Symbol Parameter Conditions Min Typ Max Unit
V
IL
Input low level voltage −
V
SS
-
0.3
− 0.3xV
DD
V
V
IH
Input high level voltage −
0.7xV
D
D
−
V
DD
+
0.3
V
hys
Schmitt trigger voltage hysteresis
(2)
−−2 − V
V
OL
Output low level voltage
(3)
V
DD
=5V
I
IO
=+5mAT
A
≤85°C
T
A
≥85°C
− 0.5
1.0
1.2
V
I
IO
=+2mAT
A
≤85°C
T
A
≥85°C
− 0.2
0.4
0.5
R
ON
Pull-up equivalent resistor
(2)(4)
V
DD
=5V 20 40 80
kΩ
V
DD
=3V 40 70 120
t
w(RSTL)out
Generated reset pulse duration Internal reset sources − 30 −μs
t
h(RSTL)in
External reset pulse hold time
(5)
− 20 −−μs
t
g(RSTL)in
Filtered glitch duration −−200 − ns
1. TA = -40°C to 85°C, unless otherwise specified.
2. Data based on characterization results, not tested in production.