Datasheet

Description ST7LITE20F2 ST7LITE25F2 ST7LITE29F2
14/170 DocID8349 Rev 7
Figure 1. General block diagram
8-bit core
ALU
ADDRESS AND DATA BUS
OSC1
OSC2
RESET
Port A
Internal
clock
Control
RAM
(384 bytes)
PA7:0
(8 bits)
V
SS
V
DD
Power
supply
Program
(8 Kbytes)
LVD
memory
PLL x 8
Ext.
1 MHz
PLL
Int.
1MHz
8-bit
Lite timer 2
Port B
SPI
PB6:0
(7 bits)
Data EEPROM
(256 bytes)
1% RC
OSC
to
16 MHz
ADC
+ Op-amp
12-bit
Auto-reload
Timer 2
CLKIN
/ 2
or PLL X4
8 MHz -> 32 MHz
Watchdog
Debug module