Datasheet

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ST7LITE20F2 ST7LITE25F2 ST7LITE29F2 Electrical characteristics
169
Figure 53. RC Osc Freq vs V
DD
@ T
A
= 25°C (calibrated with RCCR1: 3V @ 25°C)
RC oscillator and PLL characteristics
(tested for TA = -40 to +85°C) @ VDD = 2.7 to 3.3V
Symbol Parameter Conditions Min Typ Max Unit
f
RC
(1)
Internal RC oscillator
frequency
(1)
RCCR = FF (reset value), T
A
=25 °C, V
DD
=
3.0V
− 560 −
kHz
RCCR=RCCR1
(3)
,T
A
=25°C, V
DD
= 3 V − 700 −
ACC
RC
Accuracy of Internal RC
oscillator when calibrated
with RCCR=RCCR1
(2)(3)
T
A
=25°C,V
DD
=3V -2 − +2 %
T
A
=25°C,V
DD
=2.7 t 3.3V -25 − +25 %
T
A
=-40 to +85°C,V
DD
=3V -15 − 15 %
I
DD(RC)
RC oscillator current
consumption
T
A
=25°C,V
DD
=3V − 700
(2)
−μA
t
su(RC)
RC oscillator setup time T
A
=25°C,V
DD
=3V −−10
(3)
μs
f
PLL
x4 PLL input clock −−0.7
(2)
− MHz
t
LOCK
PLL Lock time
(4)
−−2 − ms
t
STAB
PLL Stabilization time
(4)
−−4 − ms
ACC
PLL
x4 PLL Accuracy
f
RC
= 1MHz@T
A
=25°C,V
DD
=2.7 to 3.3V − 0.1
(5)
− %
f
RC
= 1MHz@T
A
=40 to +85°C,V
DD
= 3V − 0.1
(5)
− %
t
w(JIT)
PLL jitter period f
RC
= 1MHz − 125
(6)
− µs
JIT
PLL
PLL jitter (Δf
CPU
/f
CPU
) −−1
(6)
− %
I
DD(PLL)
PLL current consumption T
A
=25°C − 190
(2)
−μA
1. If the RC oscillator clock is selected, to improve clock stability and frequency accuracy, it is recommended to place a
decoupling capacitor, typically 100nF, between the V
DD
and V
SS
pins as close as possible to the ST7 device.
2. Data based on characterization results, not tested in production.
3. See Section 7.1: Internal RC oscillator adjustment.
4. After the LOCKED bit is set ACC
PLL
is max. 10% until t
STAB
has elapsed. See Figure 12: PLL output frequency timing
diagram.
5. Averaged over a 4ms period. After the LOCKED bit is set, a period of t
STAB
is required to reach ACC
PLL
accuracy.
6. Guaranteed by design.
0.50
0.60
0.70
0.80
0.90
1.00
2.4 2.6 2.8 3 3.2 3.4 3.6 3.8 4
VDD (V)
Output Freq (MHz
)