Datasheet

Electrical characteristics ST7LITE20F2 ST7LITE25F2 ST7LITE29F2
124/170 DocID8349 Rev 7
Table 64. RC oscillator and PLL characteristics
(tested for T
A
= -40 to +85°C) @ V
DD
= 4.5 to 5.5 V
Symbol Parameter Conditions Min Typ Max Unit
f
RC
(1)
Internal RC oscillator
frequency
(1)
RCCR = FF (reset value), T
A
=25 °C,
V
DD
=5 V
− 760 −
kHz
RCCR = RCCR0
(2)
, T
A
=25 °C, V
DD
=5 V − 1000 −
ACC
RC
Accuracy of Internal RC
oscillator with
RCCR=RCCR0
(2)
T
A
=25° C, V
DD
=4.5 to 5.5 V -1 − +1 %
T
A
=-40 to +85 °C, V
DD
=5 V -5 − +2 %
T
A
=0 to +85° C, V
DD
=4.5 to 5.5 V -2
(3)
− +2
(3)
%
I
DD(RC)
RC oscillator current
consumption
T
A
=25° C, V
DD
=5 V − 970
(3)
−μA
t
su(RC)
RC oscillator setup time T
A
=25° C, V
DD
=5 V −−10
(2)
μs
f
PLL
x8 PLL input clock −−1
(3)
− MHz
t
LOCK
PLL Lock time
(4)
−−2 − ms
t
STAB
PLL Stabilization time
(4)
−−4 − ms
ACC
PLL
x8 PLL Accuracy
f
RC
= 1 MHz@T
A
=25° C, V
DD
=4.5 to 5.5 V − 0.1
(5)
− %
f
RC
= 1 MHz@T
A
=-40 to +85° C, V
DD
=5 V − 0.1
(5)
− %
t
w(JIT)
PLL jitter period f
RC
= 1 MHz − 125
(6)
− µs
JIT
PLL
PLL jitter (Δf
CPU
/f
CPU
) −−1
(6)
− %
I
DD(PLL)
PLL current consumption T
A
=25° C − 600
(3)
−μA
1. If the RC oscillator clock is selected, to improve clock stability and frequency accuracy, it is recommended to place a
decoupling capacitor, typically 100nF, between the V
DD
and V
SS
pins as close as possible to the ST7 device.
2. See Section 7.1: Internal RC oscillator adjustment.
3. Data based on characterization results, not tested in production.
4. After the LOCKED bit is set ACC
PLL
is max. 10% until t
STAB
has elapsed. See Figure 12: PLL output frequency timing
diagram.
5. Averaged over a 4ms period. After the LOCKED bit is set, a period of t
STAB
is required to reach ACC
PLL
accuracy.
6. Guaranteed by design.