Datasheet

Electrical characteristics ST7LITE20F2 ST7LITE25F2 ST7LITE29F2
122/170 DocID8349 Rev 7
1. Not tested in production.
2. Not tested in production. The V
DD
rise time rate condition is needed to insure a correct device power-on
and LVD reset. When the V
DD
slope is outside these values, the LVD may not ensure a proper reset of the
MCU.
Use of LVD with capacitive power supply: with this type of power supply, if power cuts occur in the
application, it is recommended to pull V
DD
down to 0 V to ensure optimum restart conditions. Refer to
circuit example in Figure 84: RESET pin protection when LVD is enabled