Datasheet

On-chip peripherals ST7LITE20F2 ST7LITE25F2 ST7LITE29F2
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11.5.4 Low power modes
Note: The A/D converter may be disabled by resetting the ADON bit. This feature allows reduced
power consumption when no conversion is needed and between single shot conversions.
11.5.5 Interrupts
None.
11.5.6 Register Description
Control/status register (ADCCSR)
Read / Write (Except Bit 7 read only)
Reset Value: 0000 0000 (00h)
• Bit 7 = EOC End of Conversion
This bit is set by hardware. It is cleared by software reading the ADCDRH register.
0: Conversion is not complete
1: Conversion complete.
• Bit 6 = SPEED ADC clock selection
This bit is set and cleared by software. It is used together with the SLOW bit to
configure the ADC clock speed. Refer to the table in the SLOW bit description.
• Bit 5 = ADON A/D Converter on
This bit is set and cleared by software.
0: A/D converter and amplifier are switched off
1: A/D converter and amplifier are switched on.
• Bits 4:3 = Reserved. Must be kept cleared.
• Bits 2:0 = CH[2:0] Channel Selection
These bits are set and cleared by software. They select the analog input to convert.
Table 44. Low power modes effects
Mode Description
WAIT No effect on A/D Converter
HALT
A/D Converter disabled.
After wakeup from HALT mode, the A/D Converter requires a stabilization time
t
STAB
(see Electrical Characteristics) before accurate conversions can be
performed.
7 0
EOC SPEED ADON 0 CH3 CH2 CH1 CH0
Table 45. Channel selection bits
Channel pin
(1)
CH2 CH1 CH0
AIN0 000
AIN1 001
AIN2 010