Datasheet

On-chip peripherals ST7LITE20F2 ST7LITE25F2 ST7LITE29F2
104/170 DocID8349 Rev 7
11.5.2 Main features
• 10-bit conversion
• Up to 7 channels with multiplexed input
• Linear successive approximation
• Data register (DR) which contains the results
• Conversion complete status flag
• On/off bit (to reduce consumption)
The block diagram is shown in Figure 49.
11.5.3 Functional description
Analog power supply
V
DDA
and V
SSA
are the high and low level reference voltage pins. In some devices (refer to
device pin out description) they are internally connected to the V
DD
and V
SS
pins.
Conversion accuracy may therefore be impacted by voltage drops and noise in the event of
heavily loaded or badly decoupled power supply lines.
Figure 49. ADC block diagram
Input voltage amplifier
The input voltage can be amplified by a factor of 8 by enabling the AMPSEL bit in the
ADCDRL register.
When the amplifier is enabled, the input range is 0 V to V
DD
/8.
CH2 CH1EOC SPEED ADON 0 CH0
ADCCSR
AIN0
AIN1
ANALOG TO DIGITAL
CONVERTER
AINx
ANALOG
MUX
D4 D3D5D9 D8 D7 D6 D2
ADCDRH
3
D1 D0
ADCDRL
00 0
AMP
SLOW
AMP
0
R
ADC
C
ADC
HOLD CONTROL
x 1 or
x 8
AMPSEL
bit
SEL
f
ADC
f
CPU
0
1
1
0
DIV 2
DIV 4
SLOW
bit
CAL