Datasheet

On-chip peripherals ST7LITE20F2 ST7LITE25F2 ST7LITE29F2
102/170 DocID8349 Rev 7
Note: While the SPIF bit is set, all writes to the SPIDR register are inhibited until the SPICSR
register is read.
• Bit 6 = WCOL Write collision status (Read only)
This bit is set by hardware when a write to the SPIDR register is done during a transmit
sequence. It is cleared by a software sequence (see Figure 47: Clearing the WCOL bit
(write collision flag) software sequence).
0: No write collision occurred
1: A write collision has been detected.
• Bit 5 = OVR SPI Overrun error (Read only)
This bit is set by hardware when the byte currently being received in the shift register is
ready to be transferred into the SPIDR register while SPIF = 1 (See Section : Overrun
condition (OVR)). An interrupt is generated if SPIE = 1 in the SPICR register. The OVR
bit is cleared by software reading the SPICSR register.
0: No overrun error
1: Overrun error detected
• Bit 4 = MODF Mode fault flag (Read only).
This bit is set by hardware when the SS pin is pulled low in master mode (see Section :
Master mode fault (MODF)). An SPI interrupt can be generated if SPIE=1 in the SPICR
register. This bit is cleared by a software sequence (An access to the SPICSR register
while MODF=1 followed by a write to the SPICR register).
0: No master mode fault detected
1: A fault in master mode has been detected
• Bit 3 = Reserved, must be kept cleared.
• Bit 2 = SOD SPI output disable
This bit is set and cleared by software. When set, it disables the alternate function of
the SPI output (MOSI in master mode / MISO in slave mode).
0: SPI output enabled (if SPE=1)
1: SPI output disabled.
• Bit 1 = SSM SS
Management.
This bit is set and cleared by software. When set, it disables the alternate function of
the SPI SS
pin and uses the SSI bit value instead. See Slave select management on
page 93.
0: Hardware management (SS
managed by external pin)
1: Software management (internal SS
signal controlled by SSI bit. External SS pin free
for general-purpose I/O).
• Bit 0 = SSI SS
Internal Mode.
This bit is set and cleared by software. It acts as a “chip select” by controlling the level
of the SS
slave select signal when the SSM bit is set.
0: Slave selected
1: Slave deselected.