Datasheet

On-chip peripherals ST7LITE20F2 ST7LITE25F2 ST7LITE29F2
100/170 DocID8349 Rev 7
11.4.7 Interrupts
Note: The SPI interrupt events are connected to the same interrupt vector (see Section 8:
Interrupts).
They generate an interrupt if the corresponding Enable Control bit is set and the interrupt
mask in the CC register is reset (RIM instruction).
11.4.8 Register description
Control register (SPICR)
Read/Write
Reset Value: 0000 xxxx (0xh)
• Bit 7 = SPIE Serial peripheral interrupt enable
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An SPI interrupt is generated whenever an End of Transfer event, Master mode
Fault or Overrun error occurs (SPIF=1, MODF=1 or OVR=1 in the SPICSR register).
• Bit 6 = SPE Serial Peripheral Output Enable
This bit is set and cleared by software. It is also cleared by hardware when, in master
mode, SS
=0 (see Master mode fault (MODF) on page 96). The SPE bit is cleared by
reset, so the SPI peripheral is not initially connected to the external pins.
0: I/O pins free for general purpose I/O
1: SPI I/O pin alternate functions enabled.
• Bit 5 = SPR2 Divider enable
This bit is set and cleared by software and is cleared by reset. It is used with the
SPR[1:0] bits to set the baud rate. Refer to Table 42: SPI master mode SCK frequency.
0: Divider by 2 enabled
1: Divider by 2 disabled
Note: This bit has no effect in slave mode.
• Bit 4 = MSTR Master mode
This bit is set and cleared by software. It is also cleared by hardware when, in master
mode, SS
=0 (see Master mode fault (MODF) on page 96).
0: Slave mode
Table 41. Interrupt events
Interrupt Event
Event
flag
Enable
control
bit
Exit
from
WAIT
Exit
from
HALT
SPI end of transfer event SPIF
SPIE
Yes Yes
Master mode fault event MODF Yes No
Overrun error OVR Yes No
7 0
SPIE SPE SPR2 MSTR CPOL CPHA SPR1 SPR0