User guide

Demo kit Hardware Configuration
EV10AQ190x-DK - User Guide 6-1
1067BX–BDC–12/11
Section 6
Demo kit Hardware Configuration
The Demo Kit could be hardware configured by changing manually some capacitor or
resistance.
This chapter describes all user settable hardware configurations.
6.1 Channel D The Channel D could be used in DC configuration mode by replacing C126 and C127 by
a 0 resistor.
Figure 6-1. Channel D Schematic
6.2 Clock Selection The ADC clock is generated by a PLL, but an external clock can be used (for frequency
different than PLL). The selection between the two clocks is done manually with a
resistor.
Remove R15 and R37 resistors and solder R36 and R50 with a 0.
Note: The VHDL code supplied permits operation at 2 GHz. A re-compilation with different tim-
ing constraints will be required for other frequencies.