User guide

FPGA CODE
5-4 EV10AQ190x-DK - User Guide
1067BX–BDC–12/11
e2v semiconductors SAS 2011
5.4 VHDL CODE A documentation of VHDL architecture is provided with the Demo Kit.
See CDROM\Documentation\FPGA Code\
DK_QUAD10_bits_FPGA_Design_Document_v1.pdf
Figure 5-6. VHDL Top level simplified block diagram
SERDES
SERDES
SERDES
SERDES
Sample Slip
Sample Slip
Sample Slip
Sample Slip
FIFO
FIFO
FIFO
FIFO
RAM
RAM
RAM
RAM
Sequencer
OUTPUT
INTERFACE
Register Bank
Acquisition Manager
10
10
10
10