User guide

FPGA CODE
EV10AQ190x-DK - User Guide 5-1
1067BX–BDC–12/11
Section 5
FPGA CODE
The FPGA code has been designed to be used with ML605 Xilinx Virtex 6 evaluation
board.
Figure 5-1. ML605 Xilinx
®
VIRTEX
®
6 Evaluation Board
Warning:
Please configure your ML605 evaluation board with correct Switch configuration.
5.1 Software
Configuration
XILINX configuration: VIRTEX-6 FPGA ML605 Evaluation Kit
Xilinx ISE Design Suite version 12 or upper with IMPACT software
5.2 FPGA Binary File A binary file is provided with the Demo Kit
 CDROM\FPGA Bin\quad10_demo_v1.1.bit
– Configuration PLL at 2 GHz with data rate into FPGA at 1Gbps
Note: because of limitation of ML605 evaluation board (LVDS max 1Gb/s in speed grade -1)
The capture of Quad 10-bit data in requires Fclock lower than 2 GHz.
Two Binaries are provided for iMPACT software
 CDROM\FPGA Bin\prog_q10.ipf (configuration of iMPACT)
 CDROM\FPGA Bin\prog_DKQ10_V1.1.mcs (PROM file)