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4-24 EV10AQ190x-DK - User Guide
1067BX–BDC–12/11
e2v semiconductors SAS 2011
4.5.4 CLOCK This sheet allows selection between the Internal PLL or external clock.
Figure 4-43. User Interface Demo Kit - Clock Settings
Note: because of limitation of ML605 evaluation board (LVDS max 1GHz in speed grade -1).
The capture of Quad 10-bit data is limited to 2 GSps.