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4-20 EV10AQ190x-DK - User Guide
1067BX–BDC–12/11
e2v semiconductors SAS 2011
Figure 4-36. FPGA Test Mode
Gain / Offset / Phase
Figure 4-37. Gain / Offset / Phase Settings
In this window, it is possible to adjust gain, offset and phase of the selected channel via
the "channel select" button on the top left of the user interface.