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4-16 EV10AQ190x-DK - User Guide
1067BX–BDC–12/11
e2v semiconductors SAS 2011
ADC mode:
 4-channels mode = the 4 ADCs work independently at Fclock/2 sampling rate (where
Fclock is the external clock signal frequency).
Figure 4-27. ADC Mode: 4-channels Mode
 2-channels mode = the 4 ADCs are interleaved 2 by 2 (A & B, C & D), the sampling
rate is equal to Fclock (where Fclock is the external clock signal frequency), the
analog inputs can be applied to A or B and respectively C or D.
Figure 4-28. ADC Mode: 2-channels Mode
 1 channel mode = the 4 ADCs are all interleaved, the sampling rate is Fclock x 2
(where Fclock is the external clock signal frequency), the analogue input can be
applied to either A, B, C or D channel.
Note: because of limitation of ML605 evaluation board (LVDS max 1GHz in speed grade -1)
The capture of Quad 10-bit data is limited to 2 GSps.