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EV10AQ190x-DK - User Guide 2-5
1067BX–BDC–12/11
 Check if acquisition is synchronous.
The ADC RAMP test procedure will set the ADC to output a ramp on each channel
these ramps are synchronous at the output of the ADC after a SYNC process has been
completed.
The FPGA RESET done during this procedure will always ensure that the 4 channels
are acquired in the FPGA synchronously.
However if the channels are found not to be synchronous as shown in Figure 2-7.
Figure 2-7. Non Synchronous Channels
Return to ADC test mode disable -> Apply and then return into ADC test mode ramp
mode -> Apply.
This will re-run the synchronization procedure of the ADC and FPGA..
Note: it is not always necessary to have the ramp patterns aligned to obtain correct data acqui-
sition using the analog inputs.