Specifications

ST72325xx
34/197
SYSTEM INTEGRITY MANAGEMENT (Cont’d)
6.4.3 Clock Security System (CSS)
The Clock Security System (CSS) protects the
ST7 against breakdowns, spikes and overfrequen-
cies occurring on the main clock source (f
OSC
). It
is based on a clock filter and a clock detection con-
trol with an internal safe oscillator (f
SFOSC
).
6.4.3.1 Clock Filter Control
The PLL has an integrated glitch filtering capability
making it possible to protect the internal clock from
overfrequencies created by individual spikes. This
feature is available only when the PLL is enabled.
If glitches occur on f
OSC
(for example, due to loose
connection or noise), the CSS filters these auto-
matically, so the internal CPU frequency (f
CPU
)
continues deliver a glitch-free signal (see Figure
20).
6.4.3.2 Clock detection Control
If the clock signal disappears (due to a broken or
disconnected resonator...), the safe oscillator de-
livers a low frequency clock signal (f
SFOSC
) which
allows the ST7 to perform some rescue opera-
tions.
Automatically, the ST7 clock source switches back
from the safe oscillator (f
SFOSC
) if the main clock
source (f
OSC
) recovers.
When the internal clock (f
CPU
) is driven by the safe
oscillator (f
SFOSC
), the application software is noti-
fied by hardware setting the CSSD bit in the SIC-
SR register. An interrupt can be generated if the
CSSIE bit has been previously set.
These two bits are described in the SICSR register
description.
6.4.4 Low Power Modes
6.4.4.1 Interrupts
The CSS orAVD interrupt events generate an in-
terrupt if the corresponding Enable Control Bit
(CSSIE or AVDIE) is set and the interrupt mask in
the CC register is reset (RIM instruction).
Figure 20. Clock Filter Function
Mode Description
WAIT
No effect on SI. CSS and AVD interrupts
cause the device to exit from Wait mode.
HALT
The SICSR register is frozen.The CSS (in-
cluding the safe oscillator) is disabled until
HALT mode is exited. The previous CSS
configuration resumes when the MCU is
woken up by an interrupt with “exit from
HALT mode” capability or from the counter
reset value when the MCU is woken up by a
RESET.
Interrupt Event
Event
Flag
Enable
Control
Bit
Exit
from
Wait
Exit
from
Halt
CSS event detection
(safe oscillator acti-
vated as main clock)
CSSD CSSIE Yes No
AVD event AVDF AVDIE Yes No
f
OSC2
f
CPU
f
OSC2
f
CPU
f
SFOSC
PLL ON
Clock Filter Function
Clock Detection Function