Specifications

ManualsBrandsADC ManualsSwitchICX-250

October 2008 Rev 4 1/197

ST72325xx

8-bit MCU with 16 to 60K Flash/ROM, ADC, CSS,

5 timers, SPI, SCI, I

C interface

Features

■ Memories

– 16K to 60K dual voltage High Density Flash

(HDFlash) or up to 32K ROM with read-out

protection capability. In-Application Program-

ming and In-Circuit Programming for HDFlash

devices

– 512 to 2048 bytes RAM

– HDFlash endurance: 100 cycles, data reten-

tion: 40 years at 85°C

■ Clock, reset and supply management

– Enhanced low voltage supervisor (LVD) for

main supply and auxiliary voltage detector

(AVD) with interrupt capability

– Clock sources: crystal/ceramic resonator os-

cillators, internal RC oscillator and bypass for

external clock

– PLL for 2x frequency multiplication

– Four Power Saving Modes: Halt, Active-Halt,

Wait and Slow

– Clock Security System

■ Interrupt management

– Nested interrupt controller

– 14 interrupt vectors plus TRAP and RESET

– Top Level Interrupt (TLI) pin on 64-pin devices

– 9/6 external interrupt lines (on 4 vectors)

■ Up to 48 I/O ports

– 48/36/32/24 multifunctional bidirectional I/O

lines

– 34/26/22/17 alternate function lines

– 16/13/12/10 high sink outputs

■ 5 timers

– Main Clock Controller with: Real time base,

Beep and Clock-out capabilities

– Configurable watchdog timer

– Two 16-bit timers with: 2 input captures, 2 out-

put compares, external clock input on one tim-

er, PWM and pulse generator modes

– 8-bit PWM Auto-reload timer with: 2 input cap-

tures, 4 PWM outputs, output compare and

time base interrupt, external clock with event

detector

■ 3 Communication interfaces

– SPI synchronous serial interface

– SCI asynchronous serial interface

–I

C multimaster interface

■ 1 Analog peripheral (low current coupling)

– 10-bit ADC with up to 16 robust input ports

■ Instruction set

– 8-bit Data Manipulation

– 63 Basic Instructions

– 17 main Addressing Modes

– 8 x 8 Unsigned Multiply Instruction

■ Development tools

– Full hardware/software development package

– DM (Debug module)

Table 1. Device summary

LQFP44

10 x 10

LQFP32

7 x 7

LQFP48

7 x 7

LQFP64

10 x 10

SDIP42

600 mil

SDIP32

400 mil

LQFP64

14 x 14

Features

ST72325S4 /

ST72325J4 / ST72325K4

ST72325S6 /

ST72325J6 / ST72325K6

ST72325J7

ST72325R9 /

ST72325AR9 /

ST72325C9 /ST72325J9

Program memory - bytes Flash/ROM 16K Flash/ROM 32K Flash 48K Flash 60K

RAM (stack) - bytes 512 (256) 1024(256) 1536 (256) 2048(256)

Operating Voltage 3.8V to 5.5V

Temp. Range up to -40°C to +125°C

Package

LQFP48(S), LQFP44/SDIP42 (J),

LQFP32/DIP32 (K)

LQFP48(S) , LQFP44/ SDIP42 (J),

LQFP32/DIP32 (K)

LQFP44 (J)

LQFP64 14x14(R), LQFP64

10x10(AR), LQFP48(C),

LQFP44 (J)

Summary of content (197 pages)

PAGE 1
ST72325xx 8-bit MCU with 16 to 60K Flash/ROM, ADC, CSS, 5 timers, SPI, SCI, I2C interface Features ■ ■ ■ ■ ■ Memories – 16K to 60K dual voltage High Density Flash (HDFlash) or up to 32K ROM with read-out protection capability.
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Table of Contents 1 DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3 REGISTER & MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4 FLASH PROGRAM MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PAGE 3
Table of Contents 8.3 WAIT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 8.4 ACTIVE-HALT AND HALT MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 8.4.1 ACTIVE-HALT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.4.2 HALT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Table of Contents 10.5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 10.5.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 10.5.3 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 10.5.4 Clock Phase and Clock Polarity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Table of Contents 12.2 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 12.2.1 Voltage Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.2.2 Current Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.2.3 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.
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Table of Contents 13.3 SOLDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 14 ST72325 DEVICE CONFIGURATION AND ORDERING INFORMATION . . . . . . . . . . . . . . . 181 14.1 FLASH OPTION BYTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 14.2 DEVICE ORDERING INFORMATION AND TRANSFER OF CUSTOMER CODE . . . . . 183 14.3 DEVELOPMENT TOOLS . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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ST72325xx 1 DESCRIPTION HALT mode when the application is in idle or stand-by state. Typical applications are consumer, home, office and industrial products. The devices feature an on-chip Debug Module (DM) to support in-circuit debugging (ICD). For a description of the DM registers, refer to the ST7 ICC Protocol Reference Manual.
PAGE 8
ST72325xx 2 PIN DESCRIPTION PE3 PE2 PE1 / RDI PE0 / TDO VDD_2 OSC1 OSC2 VSS_2 TLI EVD RESET VPP / ICCSEL PA7 (HS) / SCLI PA6 (HS) / SDAI PA5 (HS) PA4 (HS) Figure 2.
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ST72325xx Legend = Pin not connected in ST72325S devices VSS_1 VDD_1 PA3 (HS) PA2 PC7 / SS / AIN15 PC6 / SCK / ICCCLK PC5 / MOSI / AIN14 PC4 / MISO / ICCDATA PC3 (HS) / ICAP1_B PC2 (HS) / ICAP2_B PC1 / OCMP1_B / AIN13 PC0 / OCMP2_B / AIN12 VDD_0 VSS_0 48 47 46 45 44 43 42 41 40 39 38 37 36 1 2 35 3 34 ei2 33 4 32 5 ei0 31 6 ei3 30 7 29 8 28 9 27 10 26 11 ei1 25 12 13 14 15 16 17 18 19 20 21 22 23 24 AIN4 / PD4 AIN5 / PD5 VAREF VSSA MCO / AIN8 / PF0 BEEP / (HS) PF1 (HS) PF2 OCMP1_A / AIN10 / PF4 ICAP1_A
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ST72325xx PE0 / TDO VDD_2 OSC1 OSC2 VSS_2 RESET VPP / ICCSEL PA7 (HS) / SCLI PA6 (HS) / SDAI PA5 (HS) PA4 (HS) Figure 4.
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ST72325xx PD1 / AIN1 PD0 / AIN0 PB4 (HS) / ARTCLK PB3 / PWM0 PB0 / PWM3 PE1 / RDI PE0 / TDO VDD_2 Figure 5.
PAGE 12
ST72325xx PIN DESCRIPTION (Cont’d) For external pin connection guidelines, refer to See “ELECTRICAL CHARACTERISTICS” on page 142. Legend / Abbreviations for Table 2 and Table 3: Type: I = input, O = output, S = supply Input level: A = Dedicated analog input In/Output level: C = CMOS 0.3VDD/0.7VDD CT= CMOS 0.3VDD/0.
PAGE 13
ST72325xx Level OD PP 13 11 6 PD4/AIN4 I/O CT X X X X X Port D4 ADC Analog Input 4 14 14 12 7 PD5/AIN5 X X X X X Port D5 ADC Analog Input 5 19 - 4) - - - PD6/AIN6 I/O CT I/O CT X X X X X Port D6 ADC Analog Input 6 20 -4) - - - PD7/AIN7 I/O CT X X X X X Port D7 ADC Analog Input 7 21 15 15 13 8 VAREF6) I 22 16 16 14 9 VSSA6) S Analog Ground Voltage 23 - - - - VDD_36) S Digital Main Supply Voltage 24 - - - - VSS_36) S Digital Gr
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ST72325xx LQFP44 32 30 43 -4) - - - 44 -4) - - - PA1 45 33 - - - PA2 46 34 34 31 24 PA3 (HS) 47 35 35 32 25 VDD_16) 6) Input X X PA0 I/O CT I/O CT X I/O CT I/O CT HS 48 36 36 33 26 VSS_1 49 37 37 34 27 PA4 (HS) 50 38 38 35 28 PA5 (HS) 51 39 39 36 29 PA6 (HS)/SDAI 52 40 40 37 30 PA7 (HS)/SCLI PP Main function Output (after reset) OD wpu I/O CT float PC7/SS/AIN15 Output 23 Input Pin Name X X Port C7 ei0 X X Port A0 X ei0 X
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ST72325xx Table 3.
PAGE 16
ST72325xx Alternate function PP ana int wpu Input Main function Output (after reset) OD Port float Output Type DIP32 LQFP32 Pin Name Input Level Pin n° PWM Output 3 28 31 PB0/PWM3 I/O CT 29 32 PB3/PWM0 I/O CT 30 1 PB4 (HS)/ARTCLK 31 2 PD0/AIN0 I/O CT I/O CT 32 3 PD1/AIN1 I/O CT X ei2 X HS X X ei2 ei3 X Port B0 Caution: Negative current injection not allowed on this pin X X Port B3 PWM Output 0 X X Port B4 PWM-ART External Clock X X X X X Port D0 AD
PAGE 17
ST72325xx 3 REGISTER & MEMORY MAP As shown in Figure 6, the MCU is capable of addressing 64K bytes of memories and I/O registers. The available memory locations consist of 128 bytes of register locations, up to 2Kbytes of RAM and up to 60Kbytes of user program memory. The RAM space includes up to 256 bytes for the stack from 0100h to 01FFh. The highest address bytes contain the user reset and interrupt vectors. IMPORTANT: Memory locations marked as “Reserved” must never be accessed.
PAGE 18
ST72325xx Table 4.
PAGE 19
ST72325xx Address Block 002Ch 002Dh MCC Register Label MCCSR MCCBCR 002Eh to 0030h 0031h 0032h 0033h 0034h 0035h 0036h 0037h 0038h 0039h 003Ah 003Bh 003Ch 003Dh 003Eh 003Fh 0050h 0051h 0052h 0053h 0054h 0055h 0056h 0057h Reset Status Main Clock Control / Status Register Main Clock Controller: Beep Control Register 00h 00h Remarks R/W R/W Reserved Area (3 Bytes) TIMER A TACR2 TACR1 TACSR TAIC1HR TAIC1LR TAOC1HR TAOC1LR TACHR TACLR TAACHR TAACLR TAIC2HR TAIC2LR TAOC2HR TAOC2LR 0040h 0041h 0042h
PAGE 20
ST72325xx Address 0058h 0059h 005Ah 005Bh 005Ch 005Dh Block DM3) Register Label DMCR DMSR DMBK1H DMBK1L DMBK2H DMBK2L 005Eh to 006Fh 0070h 0071h 0072h 007Bh 007Ch 007Dh DM Control Register DM Status Register DM Breakpoint Register 1 High DM Breakpoint Register 1 Low DM Breakpoint Register 2 High DM Breakpoint Register 2 Low Reset Status Remarks 00h 00h 00h 00h 00h 00h R/W R/W R/W R/W R/W R/W Reserved Area (18 Bytes) ADC 0073h 0074h 0075h 0076h 0077h 0078h 0079h 007Ah Register Name PWM ART A
PAGE 21
ST72325xx 4 FLASH PROGRAM MEMORY 4.1 Introduction The ST7 dual voltage High Density Flash (HDFlash) is a non-volatile memory that can be electrically erased as a single block or by individual sectors and programmed on a Byte-by-Byte basis using an external VPP supply. The HDFlash devices can be programmed and erased off-board (plugged in a programming tool) or on-board using ICP (In-Circuit Programming) or IAP (In-Application Programming).
PAGE 22
ST72325xx FLASH PROGRAM MEMORY (Cont’d) – – – – ICCCLK: ICC output serial clock pin ICCDATA: ICC input/output serial data pin ICCSEL/VPP: programming voltage OSC1(or OSCIN): main clock input for external source (optional) – VDD: application board power supply (optional, see Figure 8, Note 3) 4.4 ICC Interface ICC needs a minimum of 4 and up to 6 pins to be connected to the programming tool (see Figure 8). These pins are: – RESET: device reset – VSS: device power supply ground Figure 8.
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ST72325xx FLASH PROGRAM MEMORY (Cont’d) 4.5 ICP (In-Circuit Programming) To perform ICP the microcontroller must be switched to ICC (In-Circuit Communication) mode by an external controller or programming tool. Depending on the ICP code downloaded in RAM, Flash memory programming can be fully customized (number of bytes to program, program locations, or selection serial communication interface for downloading).
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ST72325xx 5 CENTRAL PROCESSING UNIT 5.1 INTRODUCTION 5.3 CPU REGISTERS This CPU has a full 8-bit architecture and contains six internal registers allowing efficient 8-bit data manipulation. The six CPU registers shown in Figure 1 are not present in the memory mapping and are accessed by specific instructions. Accumulator (A) The Accumulator is an 8-bit general purpose register used to hold operands and the results of the arithmetic and logic calculations and to manipulate data.
PAGE 25
ST72325xx CENTRAL PROCESSING UNIT (Cont’d) Condition Code Register (CC) Read/Write Reset Value: 111x1xxx Bit 1 = Z Zero. 7 1 0 1 I1 H I0 N Z C The 8-bit Condition Code register contains the interrupt masks and four flags representative of the result of the instruction just executed. This register can also be handled by the PUSH and POP instructions. These bits can be individually tested and/or controlled by specific instructions. Arithmetic Management Bits Bit 4 = H Half carry.
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ST72325xx CENTRAL PROCESSING UNIT (Cont’d) Stack Pointer (SP) Read/Write Reset Value: 01 FFh 15 0 8 0 0 0 0 0 0 7 SP7 1 0 SP6 SP5 SP4 SP3 SP2 SP1 SP0 The Stack Pointer is a 16-bit register which is always pointing to the next free location in the stack. It is then decremented after data has been pushed onto the stack and incremented before data is popped from the stack (see Figure 2). Since the stack is 256 bytes deep, the 8 most significant bits are forced by hardware.
PAGE 27
ST72325xx 6 SUPPLY, RESET AND CLOCK MANAGEMENT 6.1 PHASE LOCKED LOOP The device includes a range of utility features for securing the application in critical situations (for example in case of a power brown-out), and reducing the number of external components. An overview is shown in Figure 13. For more details, refer to dedicated parametric section. If the clock frequency input to the PLL is in the range 2 to 4 MHz, the PLL can be used to multiply the frequency by two to obtain an fOSC2 of 4 to 8 MHz.
PAGE 28
ST72325xx 6.2 MULTI-OSCILLATOR (MO) 28/197 Table 6. ST7 Clock Sources External Clock Hardware Configuration Crystal/Ceramic Resonators External Clock Source In this external clock mode, a clock signal (square, sinus or triangle) with ~50% duty cycle has to drive the OSC1 pin while the OSC2 pin is tied to ground. Crystal/Ceramic Oscillators This family of oscillators has the advantage of producing a very accurate rate on the main clock of the ST7.
PAGE 29
ST72325xx 6.3 RESET SEQUENCE MANAGER (RSM) 6.3.1 Introduction The reset sequence manager includes three RESET sources as shown in Figure 15: ■ External RESET source pulse ■ Internal LVD RESET (Low Voltage Detection) ■ Internal WATCHDOG RESET These sources act on the RESET pin and it is always kept low during the delay phase. The RESET service routine vector is fixed at addresses FFFEh-FFFFh in the ST7 memory map.
PAGE 30
ST72325xx RESET SEQUENCE MANAGER (Cont’d) The RESET pin is an asynchronous signal which plays a major role in EMS performance. In a noisy environment, it is recommended to follow the guidelines mentioned in the electrical characteristics section. If the external RESET pulse is shorter than tw(RSTL)out (see short ext. Reset in Figure 16), the signal on the RESET pin may be stretched. Otherwise the delay will not be applied (see long ext. Reset in Figure 16).
PAGE 31
ST72325xx 6.4 SYSTEM INTEGRITY MANAGEMENT (SI) The System Integrity Management block contains the Low Voltage Detector (LVD) Auxiliary Voltage Detector (AVD) functions and Clock Security System (CSS). It is managed by the SICSR register. 6.4.1 Low Voltage Detector (LVD) The Low Voltage Detector function (LVD) generates a static reset when the VDD supply voltage is below a VIT- reference value. This means that it secures the power-up as well as the power-down keeping the ST7 in reset.
PAGE 32
ST72325xx SYSTEM INTEGRITY MANAGEMENT (Cont’d) 6.4.2 Auxiliary Voltage Detector (AVD) The Voltage Detector function (AVD) is based on an analog comparison between a VIT-(AVD) and VIT+(AVD) reference value and the VDD main supply or the external EVD pin voltage level (VEVD). The VIT- reference value for falling voltage is lower than the VIT+ reference value for rising voltage in order to avoid parasitic detection (hysteresis).
PAGE 33
ST72325xx SYSTEM INTEGRITY MANAGEMENT (Cont’d) 6.4.2.2 Monitoring a Voltage on the EVD pin This mode is selected by setting the AVDS bit in the SICSR register. The AVD circuitry can generate an interrupt when the AVDIE bit of the SICSR register is set. This interrupt is generated on the rising and falling edges of the comparator output.
PAGE 34
ST72325xx SYSTEM INTEGRITY MANAGEMENT (Cont’d) 6.4.3 Clock Security System (CSS) The Clock Security System (CSS) protects the ST7 against breakdowns, spikes and overfrequencies occurring on the main clock source (fOSC). It is based on a clock filter and a clock detection control with an internal safe oscillator (fSFOSC). 6.4.3.1 Clock Filter Control The PLL has an integrated glitch filtering capability making it possible to protect the internal clock from overfrequencies created by individual spikes.
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ST72325xx SYSTEM INTEGRITY MANAGEMENT (Cont’d) 6.4.5 Register Description SYSTEM INTEGRITY (SI) CONTROL/STATUS REGISTER (SICSR) Read/Write is detected by the Clock Security System (CSSD bit set). It is set and cleared by software. Reset Value: 000x 000x (00h) 0: Clock security system interrupt disabled 1: Clock security system interrupt enabled 7 0 When the CSS is disabled by OPTION BYTE, the CSSIE bit has no effect.
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ST72325xx 7 INTERRUPTS 7.
PAGE 37
ST72325xx INTERRUPTS (Cont’d) Servicing Pending Interrupts As several interrupts can be pending at the same time, the interrupt to be taken into account is determined by the following two-step process: – the highest software priority interrupt is serviced, – if several interrupts have the same software priority then the interrupt with the highest hardware priority is serviced first. Figure 22 describes this decision process. Figure 22.
PAGE 38
ST72325xx INTERRUPTS (Cont’d) 7.3 INTERRUPTS AND LOW POWER MODES 7.4 CONCURRENT & NESTED MANAGEMENT All interrupts allow the processor to exit the WAIT low power mode. On the contrary, only external and other specified interrupts allow the processor to exit from the HALT modes (see column “Exit from HALT” in “Interrupt Mapping” table).
PAGE 39
ST72325xx INTERRUPTS (Cont’d) INTERRUPT SOFTWARE PRIORITY REGISTERS (ISPRX) Read/Write (bit 7:4 of ISPR3 are read only) Reset Value: 1111 1111 (FFh) 7.
PAGE 40
ST72325xx INTERRUPTS (Cont’d) Table 8.
PAGE 41
ST72325xx INTERRUPTS (Cont’d) Table 9. Interrupt Mapping N° Source Block RESET TRAP Register Label Description Reset N/A Software interrupt 0 TLI 1 MCC/RTC/ CSS 2 ei0 External interrupt port A3..0 3 ei1 External interrupt port F2..0 4 ei2 External interrupt port B3..0 5 ei3 External interrupt port B7..
PAGE 42
ST72325xx INTERRUPTS (Cont’d) Figure 25. External Interrupt Control bits PORT A3 INTERRUPT PAOR.3 PADDR.3 EICR IS20 IS21 ei0 INTERRUPT SOURCE SENSITIVITY PA3 CONTROL IPA BIT PORT F [2:0] INTERRUPTS EICR IS20 PFOR.2 PFDDR.2 IS21 SENSITIVITY PF2 CONTROL PORT B [3:0] INTERRUPTS PBOR.3 PBDDR.3 IS10 IS11 SENSITIVITY CONTROL IPB BIT PBOR.4 PBDDR.
PAGE 43
ST72325xx 7.7 EXTERNAL INTERRUPT CONTROL REGISTER (EICR) Read/Write Reset Value: 0000 0000 (00h) - ei0 (port A3) External Interrupt Sensitivity 7 IS11 0 IS10 IPB IS21 IS20 IPA TLIS TLIE Bit 7:6 = IS1[1:0] ei2 and ei3 sensitivity The interrupt sensitivity, defined using the IS1[1:0] bits, is applied to the following external interrupts: - ei2 (port B3..
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ST72325xx INTERRUPTS (Cont’d) Table 10. Nested Interrupts Register Map and Reset Values Address (Hex.
PAGE 45
ST72325xx 8 POWER SAVING MODES 8.1 INTRODUCTION 8.2 SLOW MODE To give a large measure of flexibility to the application in terms of power consumption, four main power saving modes are implemented in the ST7 (see Figure 26): SLOW, WAIT (SLOW WAIT), ACTIVE HALT and HALT. After a RESET the normal operating mode is selected by default (RUN mode).
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ST72325xx POWER SAVING MODES (Cont’d) 8.3 WAIT MODE WAIT mode places the MCU in a low power consumption mode by stopping the CPU. This power saving mode is selected by calling the ‘WFI’ instruction. All peripherals remain active. During WAIT mode, the I[1:0] bits of the CC register are forced to ‘10’, to enable all interrupts. All other registers and memory remain unchanged.
PAGE 47
ST72325xx POWER SAVING MODES (Cont’d) 8.4 ACTIVE-HALT AND HALT MODES ACTIVE-HALT and HALT modes are the two lowest power consumption modes of the MCU. They are both entered by executing the ‘HALT’ instruction. The decision to enter either in ACTIVE-HALT or HALT mode is given by the MCC/RTC interrupt enable flag (OIE bit in MCCSR register). the interrupt occurs (tDELAY = 256 or 4096 tCPU delay depending on option byte). Otherwise, the ST7 enters HALT mode for the remaining tDELAY period. Figure 29.
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ST72325xx POWER SAVING MODES (Cont’d) 8.4.2 HALT MODE The HALT mode is the lowest power consumption mode of the MCU. It is entered by executing the ‘HALT’ instruction when the OIE bit of the Main Clock Controller Status register (MCCSR) is cleared (see section 10.2 on page 61 for more details on the MCCSR register). The MCU can exit HALT mode on reception of either a specific interrupt (see Table 9, “Interrupt Mapping,” on page 41) or a RESET.
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ST72325xx POWER SAVING MODES (Cont’d) 8.4.2.1 Halt Mode Recommendations – Make sure that an external event is available to wake up the microcontroller from Halt mode. – When using an external interrupt to wake up the microcontroller, reinitialize the corresponding I/O as “Input Pull-up with Interrupt” before executing the HALT instruction. The main reason for this is that the I/O may be wrongly configured due to external interference or by an unforeseen logical condition.
PAGE 50
ST72325xx 9 I/O PORTS 9.1 INTRODUCTION The I/O ports offer different functional modes: – transfer of data through digital inputs and outputs and for specific pins: – external interrupt generation – alternate signal input/output for the on-chip peripherals. An I/O port contains up to 8 pins. Each pin can be programmed independently as digital input (with or without interrupt generation) or digital output. 9.
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ST72325xx I/O PORTS (Cont’d) Figure 33. I/O Port General Block Diagram ALTERNATE OUTPUT REGISTER ACCESS 1 VDD 0 P-BUFFER (see table below) ALTERNATE ENABLE PULL-UP (see table below) DR VDD DDR PULL-UP CONDITION DATA BUS OR PAD If implemented OR SEL N-BUFFER DIODES (see table below) DDR SEL DR SEL ANALOG INPUT CMOS SCHMITT TRIGGER 1 0 ALTERNATE INPUT EXTERNAL INTERRUPT SOURCE (eix) Table 11.
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ST72325xx I/O PORTS (Cont’d) Table 12.
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ST72325xx I/O PORTS (Cont’d) CAUTION: The alternate function must not be activated as long as the pin is configured as input with interrupt, in order to avoid generating spurious interrupts. Analog alternate function When the pin is used as an ADC input, the I/O must be configured as floating input. The analog multiplexer (controlled by the ADC registers) switches the analog voltage present on the selected pin to the common analog rail which is connected to the ADC input.
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ST72325xx I/O PORTS (Cont’d) 9.5.1 I/O Port Implementation The I/O port register configurations are summarised as follows.
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ST72325xx I/O PORTS (Cont’d) Table 14. I/O Port Register Map and Reset Values Address (Hex.
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ST72325xx 10 ON-CHIP PERIPHERALS 10.1 WATCHDOG TIMER (WDG) 10.1.1 Introduction The Watchdog timer is used to detect the occurrence of a software fault, usually generated by external interference or by unforeseen logical conditions, which causes the application program to abandon its normal sequence. The Watchdog circuit generates an MCU reset on expiry of a programmed time period, unless the program refreshes the counter’s contents before the T6 bit becomes cleared. 10.1.
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ST72325xx WATCHDOG TIMER (Cont’d) 10.1.4 How to Program the Watchdog Timeout Figure 2 shows the linear relationship between the 6-bit value to be loaded in the Watchdog Counter (CNT) and the resulting timeout duration in milliseconds. This can be used for a quick calculation without taking the timing variations into account. If more precision is needed, use the formulae in Figure 3. Caution: When writing to the WDGCR register, always write 1 in the T6 bit to avoid generating an immediate reset.
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ST72325xx WATCHDOG TIMER (Cont’d) Figure 37. Exact Timeout Duration (tmin and tmax) WHERE: tmin0 = (LSB + 128) x 64 x tOSC2 tmax0 = 16384 x tOSC2 tOSC2 = 125ns if fOSC2=8 MHz CNT = Value of T[5:0] bits in the WDGCR register (6 bits) MSB and LSB are values from the table below depending on the timebase selected by the TB[1:0] bits in the MCCSR register TB1 Bit TB0 Bit (MCCSR Reg.) (MCCSR Reg.
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ST72325xx WATCHDOG TIMER (Cont’d) 10.1.5 Low Power Modes Mode SLOW WAIT Description No effect on Watchdog. No effect on Watchdog. OIE bit in MCCSR register WDGHALT bit in Option Byte 0 0 0 1 1 x HALT No Watchdog reset is generated. The MCU enters Halt mode. The Watchdog counter is decremented once and then stops counting and is no longer able to generate a watchdog reset until the MCU receives an external interrupt or a reset.
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ST72325xx Table 15. Watchdog Timer Register Map and Reset Values Address (Hex.
PAGE 61
ST72325xx 10.2 MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK AND BEEPER (MCC/RTC) The Main Clock Controller consists of three different functions: ■ a programmable CPU clock prescaler ■ a clock-out signal to supply external devices ■ a real time clock timer with interrupt capability Each function can be used independently and simultaneously. 10.2.1 Programmable CPU Clock Prescaler The programmable CPU clock prescaler supplies the clock for the ST7 CPU and its internal peripherals.
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ST72325xx MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK (Cont’d) 10.2.5 Low Power Modes Bit 6:5 = CP[1:0] CPU clock prescaler Mode Description These bits select the CPU clock prescaler which is No effect on MCC/RTC peripheral. applied in the different slow modes. Their action is WAIT MCC/RTC interrupt cause the device to exit conditioned by the setting of the SMS bit. These from WAIT mode.
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ST72325xx MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK (Cont’d) MCC BEEP CONTROL REGISTER (MCCBCR) Bit 0 = OIF Oscillator interrupt flag This bit is set by hardware and cleared by software Read/Write reading the MCCSR register. It indicates when set Reset Value: 0000 0000 (00h) that the main oscillator has reached the selected elapsed time (TB1:0).
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ST72325xx 10.3 PWM AUTO-RELOAD TIMER (ART) 10.3.1 Introduction The Pulse Width Modulated Auto-Reload Timer on-chip peripheral consists of an 8-bit auto reload counter with compare/capture capabilities and of a 7-bit prescaler clock source.
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ST72325xx ON-CHIP PERIPHERALS (Cont’d) 10.3.2 Functional Description Counter The free running 8-bit counter is fed by the output of the prescaler, and is incremented on every rising edge of the clock signal. It is possible to read or write the contents of the counter on the fly by reading or writing the Counter Access register (ARTCAR). When a counter overflow occurs, the counter is automatically reloaded with the contents of the ARTARR register (the prescaler is not affected).
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ST72325xx ON-CHIP PERIPHERALS (Cont’d) Independent PWM signal generation This mode allows up to four Pulse Width Modulated signals to be generated on the PWMx output pins with minimum core processing overhead. This function is stopped during HALT mode. Each PWMx output signal can be selected independently using the corresponding OEx bit in the PWM Control register (PWMCR). When this bit is set, the corresponding I/O pin is configured as output push-pull alternate function.
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ST72325xx ON-CHIP PERIPHERALS (Cont’d) Output compare and Time base interrupt On overflow, the OVF flag of the ARTCSR register is set and an overflow interrupt request is generated if the overflow interrupt enable bit, OIE, in the ARTCSR register, is set. The OVF flag must be reset by the user software. This interrupt can be used as a time base in the application.
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ST72325xx ON-CHIP PERIPHERALS (Cont’d) Input capture function This mode allows the measurement of external signal pulse widths through ARTICRx registers. Each input capture can generate an interrupt independently on a selected input signal transition. This event is flagged by a set of the corresponding CFx bits of the Input Capture Control/Status register (ARTICCSR). These input capture interrupts are enabled through the CIEx bits of the ARTICCSR register.
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ST72325xx ON-CHIP PERIPHERALS (Cont’d) 10.3.3 Register Description 0: New transition not yet reached 1: Transition reached CONTROL / STATUS REGISTER (ARTCSR) Read/Write Reset Value: 0000 0000 (00h) 7 EXCL 0 CC2 CC1 CC0 TCE FCRL OIE COUNTER ACCESS REGISTER (ARTCAR) Read/Write Reset Value: 0000 0000 (00h) OVF 7 Bit 7 = EXCL External Clock This bit is set and cleared by software. It selects the input clock for the 7-bit prescaler. 0: CPU clock. 1: External clock.
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ST72325xx ON-CHIP PERIPHERALS (Cont’d) PWM CONTROL REGISTER (PWMCR) Read/Write Reset Value: 0000 0000 (00h) DUTY CYCLE REGISTERS (PWMDCRx) Read/Write Reset Value: 0000 0000 (00h) 7 OE3 OE2 OE1 OE0 OP3 OP2 OP1 0 7 OP0 DC7 Bit 7:4 = OE[3:0] PWM Output Enable These bits are set and cleared by software. They enable or disable the PWM output channels independently acting on the corresponding I/O pin. 0: PWM output disabled. 1: PWM output enabled.
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ST72325xx ON-CHIP PERIPHERALS (Cont’d) INPUT CAPTURE CONTROL / STATUS REGISTER (ARTICCSR) Read/Write Reset Value: 0000 0000 (00h) INPUT CAPTURE REGISTERS (ARTICRx) Read only Reset Value: 0000 0000 (00h) 7 7 IC7 0 0 0 0 CS2 CS1 CIE2 CIE1 CF2 IC6 IC5 IC4 IC3 IC2 IC1 IC0 CF1 Bit 7:6 = Reserved, always read as 0. Bit 5:4 = CS[2:1] Capture Sensitivity These bits are set and cleared by software. They determine the trigger event polarity on the corresponding input capture channel.
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ST72325xx PWM AUTO-RELOAD TIMER (Cont’d) Table 17. PWM Auto-Reload Timer Register Map and Reset Values Address (Hex.
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ST72325xx 10.4 16-BIT TIMER 10.4.1 Introduction The timer consists of a 16-bit free-running counter driven by a programmable prescaler. It may be used for a variety of purposes, including pulse length measurement of up to two input signals (input capture) or generation of up to two output waveforms (output compare and PWM). Pulse lengths and waveform periods can be modulated from a few microseconds to several milliseconds using the timer prescaler and the CPU clock prescaler.
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ST72325xx 16-BIT TIMER (Cont’d) Figure 45.
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ST72325xx 16-BIT TIMER (Cont’d) 16-bit read sequence: (from either the Counter Register or the Alternate Counter Register). Beginning of the sequence At t0 Read MS Byte LS Byte is buffered Other instructions Read At t0 +Δt LS Byte Returns the buffered LS Byte value at t0 Sequence completed The user must read the MS Byte first, then the LS Byte value is buffered automatically.
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ST72325xx 16-BIT TIMER (Cont’d) Figure 46. Counter Timing Diagram, Internal Clock Divided by 2 CPU CLOCK INTERNAL RESET TIMER CLOCK COUNTER REGISTER FFFD FFFE FFFF 0000 0001 0002 0003 TIMER OVERFLOW FLAG (TOF) Figure 47. Counter Timing Diagram, Internal Clock Divided by 4 CPU CLOCK INTERNAL RESET TIMER CLOCK COUNTER REGISTER FFFC FFFD 0000 0001 TIMER OVERFLOW FLAG (TOF) Figure 48.
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ST72325xx 16-BIT TIMER (Cont’d) 10.4.3.3 Input Capture In this section, the index, i, may be 1 or 2 because there are two input capture functions in the 16-bit timer. The two 16-bit input capture registers (IC1R and IC2R) are used to latch the value of the free running counter after a transition is detected on the ICAPi pin (see Figure 5). ICiR MS Byte ICiHR LS Byte ICiLR ICiR register is a read-only register.
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ST72325xx 16-BIT TIMER (Cont’d) Figure 49. Input Capture Block Diagram ICAP1 pin ICAP2 pin (Control Register 1) CR1 EDGE DETECT CIRCUIT2 EDGE DETECT CIRCUIT1 ICIE IEDG1 (Status Register) SR IC2R Register IC1R Register ICF1 ICF2 0 16-BIT FREE RUNNING COUNTER CC1 CC0 IEDG2 Figure 50. Input Capture Timing Diagram TIMER CLOCK FF01 FF02 FF03 ICAPi PIN ICAPi FLAG ICAPi REGISTER Note: The rising edge is the active edge.
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ST72325xx 16-BIT TIMER (Cont’d) 10.4.3.4 Output Compare In this section, the index, i, may be 1 or 2 because there are two output compare functions in the 16bit timer. This function can be used to control an output waveform or indicate when a period of time has elapsed.
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ST72325xx 16-BIT TIMER (Cont’d) Notes: 1. After a processor write cycle to the OCiHR register, the output compare function is inhibited until the OCiLR register is also written. 2. If the OCiE bit is not set, the OCMPi pin is a general I/O port and the OLVLi bit will not appear when a match is found but an interrupt could be generated if the OCIE bit is set. 3.
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ST72325xx 16-BIT TIMER (Cont’d) Figure 52. Output Compare Timing Diagram, fTIMER = fCPU/2 INTERNAL CPU CLOCK TIMER CLOCK COUNTER REGISTER 2ECF 2ED0 OUTPUT COMPARE REGISTER i (OCRi) 2ED1 2ED2 2ED3 2ED4 2ED3 OUTPUT COMPARE FLAG i (OCFi) OCMPi PIN (OLVLi = 1) Figure 53.
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ST72325xx 16-BIT TIMER (Cont’d) 10.4.3.5 One Pulse Mode One Pulse mode enables the generation of a pulse when an external event occurs. This mode is selected via the OPM bit in the CR2 register. The One Pulse mode uses the Input Capture1 function and the Output Compare1 function. Procedure: To use One Pulse mode: 1. Load the OC1R register with the value corresponding to the length of the pulse (see the formula in the opposite column). 2.
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ST72325xx 16-BIT TIMER (Cont’d) Figure 54. One Pulse Mode Timing Example COUNTER 2ED3 01F8 IC1R 01F8 FFFC FFFD FFFE 2ED0 2ED1 2ED2 FFFC FFFD 2ED3 ICAP1 OLVL2 OCMP1 OLVL1 OLVL2 compare1 Note: IEDG1 = 1, OC1R = 2ED0h, OLVL1 = 0, OLVL2 = 1 Figure 55.
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ST72325xx 16-BIT TIMER (Cont’d) 10.4.3.6 Pulse Width Modulation Mode Pulse Width Modulation (PWM) mode enables the generation of a signal with a frequency and pulse length determined by the value of the OC1R and OC2R registers. Pulse Width Modulation mode uses the complete Output Compare 1 function plus the OC2R register, and so this functionality can not be used when PWM mode is activated. In PWM mode, double buffering is implemented on the output compare registers.
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ST72325xx 16-BIT TIMER (Cont’d) 10.4.4 Low Power Modes Mode WAIT HALT Description No effect on 16-bit Timer. Timer interrupts cause the device to exit from WAIT mode. 16-bit Timer registers are frozen. In HALT mode, the counter stops counting until Halt mode is exited. Counting resumes from the previous count when the MCU is woken up by an interrupt with “exit from HALT mode” capability or from the counter reset value when the MCU is woken up by a RESET.
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ST72325xx 16-BIT TIMER (Cont’d) 10.4.7 Register Description Each Timer is associated with three control and status registers, and with six pairs of data registers (16-bit values) relating to the two input captures, the two output compares, the counter and the alternate counter. CONTROL REGISTER 1 (CR1) Read/Write Reset Value: 0000 0000 (00h) 7 0 Bit 4 = FOLV2 Forced Output Compare 2. This bit is set and cleared by software. 0: No effect on the OCMP2 pin.
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ST72325xx 16-BIT TIMER (Cont’d) CONTROL REGISTER 2 (CR2) Read/Write Reset Value: 0000 0000 (00h) 7 0 OC1E OC2E OPM PWM CC1 CC0 IEDG2 EXEDG Bit 7 = OC1E Output Compare 1 Pin Enable. This bit is used only to output the signal from the timer on the OCMP1 pin (OLV1 in Output Compare mode, both OLV1 and OLV2 in PWM and one-pulse mode). Whatever the value of the OC1E bit, the Output Compare 1 function of the timer remains active. 0: OCMP1 pin alternate function disabled (I/O pin free for general-purpose I/O).
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ST72325xx 16-BIT TIMER (Cont’d) CONTROL/STATUS REGISTER (CSR) Read/Write (bits 7:3 read only) Reset Value: xxxx x0xx (xxh) Note: Reading or writing the ACLR register does not clear TOF. 7 ICF1 0 OCF1 TOF ICF2 OCF2 TIMD 0 0 Bit 7 = ICF1 Input Capture Flag 1. 0: No input capture (reset value). 1: An input capture has occurred on the ICAP1 pin or the counter has reached the OC2R value in PWM mode.
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ST72325xx 16-BIT TIMER (Cont’d) INPUT CAPTURE 1 HIGH REGISTER (IC1HR) Read Only Reset Value: Undefined This is an 8-bit read only register that contains the high part of the counter value (transferred by the input capture 1 event). OUTPUT COMPARE 1 HIGH REGISTER (OC1HR) Read/Write Reset Value: 1000 0000 (80h) This is an 8-bit register that contains the high part of the value to be compared to the CHR register.
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ST72325xx 16-BIT TIMER (Cont’d) OUTPUT COMPARE 2 HIGH REGISTER (OC2HR) Read/Write Reset Value: 1000 0000 (80h) This is an 8-bit register that contains the high part of the value to be compared to the CHR register. ALTERNATE COUNTER HIGH REGISTER (ACHR) Read Only Reset Value: 1111 1111 (FFh) This is an 8-bit register that contains the high part of the counter value.
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ST72325xx 16-BIT TIMER (Cont’d) Table 19. 16-Bit Timer Register Map and Reset Values Address (Hex.
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ST72325xx 10.5 SERIAL PERIPHERAL INTERFACE (SPI) 10.5.1 Introduction The Serial Peripheral Interface (SPI) allows fullduplex, synchronous, serial communication with external devices. An SPI system may consist of a master and one or more slaves however the SPI interface can not be a master in a multi-master system. 10.5.2 Main Features ■ Full duplex synchronous transfers (on 3 lines) ■ Simplex synchronous transfers (on 2 lines) ■ Master or slave operation ■ Six master mode frequencies (fCPU/4 max.
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ST72325xx SERIAL PERIPHERAL INTERFACE (Cont’d) – SS: Slave select: This input signal acts as a ‘chip select’ to let the SPI master communicate with slaves individually and to avoid contention on the data lines. Slave SS inputs can be driven by standard I/O ports on the master MCU. 10.5.3.1 Functional Description A basic example of interconnections between a single master and a single slave is illustrated in Figure 57. The MOSI pins are connected together and the MISO pins are connected together.
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ST72325xx SERIAL PERIPHERAL INTERFACE (Cont’d) 10.5.3.2 Slave Select Management As an alternative to using the SS pin to control the Slave Select signal, the application can choose to manage the Slave Select signal by software. This is configured by the SSM bit in the SPICSR register (see Figure 59) In software management, the external SS pin is free for other application uses and the internal SS signal level is driven by writing to the SSI bit in the SPICSR register.
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ST72325xx SERIAL PERIPHERAL INTERFACE (Cont’d) 10.5.3.3 Master Mode Operation In master mode, the serial clock is output on the SCK pin. The clock frequency, polarity and phase are configured by software (refer to the description of the SPICSR register). Note: The idle state of SCK must correspond to the polarity selected in the SPICSR register (by pulling up SCK if CPOL=1 or pulling down SCK if CPOL=0).
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ST72325xx SERIAL PERIPHERAL INTERFACE (Cont’d) 10.5.4 Clock Phase and Clock Polarity Four possible timing relationships may be chosen by software, using the CPOL and CPHA bits (See Figure 60). Note: The idle state of SCK must correspond to the polarity selected in the SPICSR register (by pulling up SCK if CPOL=1 or pulling down SCK if CPOL=0).
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ST72325xx SERIAL PERIPHERAL INTERFACE (Cont’d) 10.5.5 Error Flags 10.5.5.1 Master Mode Fault (MODF) Master mode fault occurs when the master device has its SS pin pulled low. When a Master mode fault occurs: – The MODF bit is set and an SPI interrupt request is generated if the SPIE bit is set. – The SPE bit is reset. This blocks all output from the device and disables the SPI peripheral. – The MSTR bit is reset, thus forcing the device into slave mode.
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ST72325xx SERIAL PERIPHERAL INTERFACE (Cont’d) 10.5.5.4 Single Master Systems A typical single master system may be configured, using an MCU as the master and four MCUs as slaves (see Figure 62). The master device selects the individual slave devices by using four pins of a parallel port to control the four SS pins of the slave devices. The SS pins are pulled high during reset since the master device ports will be forced to be inputs at that time, thus disabling the slave devices.
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ST72325xx SERIAL PERIPHERAL INTERFACE (Cont’d) 10.5.6 Low Power Modes Mode WAIT HALT Description No effect on SPI. SPI interrupt events cause the device to exit from WAIT mode. SPI registers are frozen. In HALT mode, the SPI is inactive. SPI operation resumes when the MCU is woken up by an interrupt with “exit from HALT mode” capability. The data received is subsequently read from the SPIDR register when the software is running (interrupt vector fetching).
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ST72325xx SERIAL PERIPHERAL INTERFACE (Cont’d) 10.5.8 Register Description CONTROL REGISTER (SPICR) Read/Write Reset Value: 0000 xxxx (0xh) 7 SPIE 0 SPE SPR2 MSTR CPOL CPHA SPR1 SPR0 Bit 7 = SPIE Serial Peripheral Interrupt Enable. This bit is set and cleared by software. 0: Interrupt is inhibited 1: An SPI interrupt is generated whenever SPIF=1, MODF=1 or OVR=1 in the SPICSR register Bit 6 = SPE Serial Peripheral Output Enable. This bit is set and cleared by software.
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ST72325xx SERIAL PERIPHERAL INTERFACE (Cont’d) CONTROL/STATUS REGISTER (SPICSR) Read/Write (some bits Read Only) Reset Value: 0000 0000 (00h) 7 SPIF Bit 3 = Reserved, must be kept cleared. 0 WCOL OVR MODF - SOD SSM SSI Bit 7 = SPIF Serial Peripheral Data Transfer Flag (Read only). This bit is set by hardware when a transfer has been completed. An interrupt is generated if SPIE=1 in the SPICR register.
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ST72325xx SERIAL PERIPHERAL INTERFACE (Cont’d) Table 21. SPI Register Map and Reset Values Address (Hex.
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ST72325xx 10.6 SERIAL COMMUNICATIONS INTERFACE (SCI) 10.6.1 Introduction The Serial Communications Interface (SCI) offers a flexible means of full-duplex data exchange with external equipment requiring an industry standard NRZ asynchronous serial data format. The SCI offers a very wide range of baud rates using two baud rate generator systems. 10.6.
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ST72325xx SERIAL COMMUNICATIONS INTERFACE (Cont’d) Figure 63.
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ST72325xx SERIAL COMMUNICATIONS INTERFACE (Cont’d) 10.6.4 Functional Description The block diagram of the Serial Control Interface, is shown in Figure 1. It contains six dedicated registers: – Two control registers (SCICR1 & SCICR2) – A status register (SCISR) – A baud rate register (SCIBRR) – An extended prescaler receiver register (SCIERPR) – An extended prescaler transmitter register (SCIETPR) Refer to the register descriptions in Section 0.1.7 for the definitions of each bit. 10.6.4.
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ST72325xx SERIAL COMMUNICATIONS INTERFACE (Cont’d) 10.6.4.2 Transmitter The transmitter can send data words of either 8 or 9 bits depending on the M bit status. When the M bit is set, word length is 9 bits and the 9th bit (the MSB) has to be stored in the T8 bit in the SCICR1 register. Character Transmission During an SCI transmission, data shifts out least significant bit first on the TDO pin.
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ST72325xx SERIAL COMMUNICATIONS INTERFACE (Cont’d) 10.6.4.3 Receiver The SCI can receive data words of either 8 or 9 bits. When the M bit is set, word length is 9 bits and the MSB is stored in the R8 bit in the SCICR1 register. Character reception During a SCI reception, data shifts in least significant bit first through the RDI pin. In this mode, the SCIDR register consists or a buffer (RDR) between the internal bus and the received shift register (see Figure 1.).
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ST72325xx SERIAL COMMUNICATIONS INTERFACE (Cont’d) Figure 65.
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ST72325xx SERIAL COMMUNICATIONS INTERFACE (Cont’d) Framing Error A framing error is detected when: – The stop bit is not recognized on reception at the expected time, following either a de-synchronization or excessive noise. – A break is received. When the framing error is detected: – the FE bit is set by hardware – Data is transferred from the Shift register to the SCIDR register. – No interrupt is generated. However this bit rises at the same time as the RDRF bit which itself generates an interrupt.
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ST72325xx SERIAL COMMUNICATIONS INTERFACE (Cont’d) 10.6.4.7 Parity Control Parity control (generation of parity bit in transmission and parity checking in reception) can be enabled by setting the PCE bit in the SCICR1 register. Depending on the frame length defined by the M bit, the possible SCI frame formats are as listed in Table 1. Table 22.
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ST72325xx SERIAL COMMUNICATIONS INTERFACE (Cont’d) 10.6.4.9 Clock Deviation Causes The causes which contribute to the total deviation are: – DTRA: Deviation due to transmitter error (Local oscillator error of the transmitter or the transmitter is transmitting at a different baud rate). – DQUANT: Error due to the baud rate quantization of the receiver.
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ST72325xx SERIAL COMMUNICATIONS INTERFACE (Cont’d) 10.6.5 Low Power Modes 10.6.6 Interrupts The SCI interrupt events are connected to the Mode Description same interrupt vector. No effect on SCI. These events generate an interrupt if the correWAIT SCI interrupts cause the device to exit from sponding Enable Control Bit is set and the interWait mode. rupt mask in the CC register is reset (RIM instrucSCI registers are frozen. tion).
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ST72325xx SERIAL COMMUNICATIONS INTERFACE (Cont’d) 10.6.7 Register Description Note: The IDLE bit is not set again until the RDRF bit has been set itself (that is, a new idle line ocSTATUS REGISTER (SCISR) curs). Read Only Reset Value: 1100 0000 (C0h) Bit 3 = OR Overrun error. 7 0 This bit is set by hardware when the word currently being received in the shift register is ready to be TDRE TC RDRF IDLE OR NF FE PE transferred into the RDR register while RDRF = 1.
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ST72325xx SERIAL COMMUNICATIONS INTERFACE (Cont’d) CONTROL REGISTER 1 (SCICR1) Read/Write Bit 3 = WAKE Wake-Up method. This bit determines the SCI Wake-Up method, it is Reset Value: x000 0000 (x0h) set or cleared by software. 0: Idle Line 7 0 1: Address Mark R8 T8 SCID M WAKE PCE PS PIE Bit 7 = R8 Receive data bit 8. This bit is used to store the 9th bit of the received word when M = 1. Bit 6 = T8 Transmit data bit 8. This bit is used to store the 9th bit of the transmitted word when M = 1.
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ST72325xx SERIAL COMMUNICATIONS INTERFACE (Cont’d) CONTROL REGISTER 2 (SCICR2) Notes: Read/Write – During transmission, a “0” pulse on the TE bit (“0” followed by “1”) sends a preamble (idle line) Reset Value: 0000 0000 (00h) after the current word. 7 0 – When TE is set there is a 1 bit-time delay before the transmission starts. TIE TCIE RIE ILIE TE RE RWU SBK CAUTION: The TDO pin is free for general purpose I/O only when the TE and RE bits are both cleared (or if TE is never set).
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ST72325xx SERIAL COMMUNICATIONS INTERFACE (Cont’d) DATA REGISTER (SCIDR) Read/Write Reset Value: Undefined Contains the Received or Transmitted data character, depending on whether it is read from or written to. 7 0 DR7 DR6 DR5 DR4 DR3 DR2 DR1 DR0 The Data register performs a double function (read and write) since it is composed of two registers, one for transmission (TDR) and one for reception (RDR).
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ST72325xx SERIAL COMMUNICATIONS INTERFACE (Cont’d) EXTENDED RECEIVE PRESCALER DIVISION REGISTER (SCIERPR) Read/Write Reset Value: 0000 0000 (00h) Allows setting of the Extended Prescaler rate division factor for the receive circuit. 7 0 EXTENDED TRANSMIT PRESCALER DIVISION REGISTER (SCIETPR) Read/Write Reset Value:0000 0000 (00h) Allows setting of the External Prescaler rate division factor for the transmit circuit.
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ST72325xx SERIAL COMMUNICATION INTERFACE (Cont’d) Table 24. SCI Register Map and Reset Values Address (Hex.
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ST72325xx 10.7 I2C BUS INTERFACE (I2C) 10.7.1 Introduction The I2C Bus Interface serves as an interface between the microcontroller and the serial I2C bus. It provides both multimaster and slave functions, and controls all I2C bus-specific sequencing, protocol, arbitration and timing. It supports fast I2C mode (400kHz). 10.7.2 Main Features 2 ■ Parallel-bus/I C protocol converter ■ Multi-master capability ■ 7-bit/10-bit Addressing ■ SMBus V1.
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ST72325xx I2C BUS INTERFACE (Cont’d) Acknowledge may be enabled and disabled by software. The I2C interface address and/or general call address can be selected by software. The speed of the I2C interface may be selected between Standard (up to 100KHz) and Fast I2C (up to 400KHz). SDA/SCL Line Control Transmitter mode: the interface holds the clock line low before transmission to wait for the microcontroller to write the byte in the Data Register.
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ST72325xx I2C BUS INTERFACE (Cont’d) 10.7.4 Functional Description Refer to the CR, SR1 and SR2 registers in Section 10.7.7. for the bit definitions. By default the I2C interface operates in Slave mode (M/SL bit is cleared) except when it initiates a transmit or receive sequence. First the interface frequency must be configured using the FRi bits in the OAR2 register. 10.7.4.
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ST72325xx I2C INTERFACE (Cont’d) How to release the SDA / SCL lines Set and subsequently clear the STOP bit while BTF is set. The SDA/SCL lines are released after the transfer of the current byte. SMBus Compatibility ST7 I2C is compatible with SMBus V1.1 protocol. It supports all SMBus adressing modes, SMBus bus protocols and CRC-8 packet error checking. Refer to AN1713: SMBus Slave Driver For ST7 I2C Peripheral. 10.7.4.
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ST72325xx I2C BUS INTERFACE (Cont’d) Master Transmitter Following the address transmission and after SR1 register has been read, the master sends bytes from the DR register to the SDA line via the internal shift register. The master waits for a read of the SR1 register followed by a write in the DR register, holding the SCL line low (see Figure 69 Transfer sequencing EV8). When the acknowledge bit is received, the interface sets: – EVF and BTF bits with an interrupt if the ITE bit is set.
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ST72325xx I2C BUS INTERFACE (Cont’d) Figure 69. Transfer Sequencing 7-bit Slave receiver: S Address A Data1 A Data2 EV1 A EV2 EV2 ..... DataN A P EV2 EV4 7-bit Slave transmitter: S Address A Data1 A EV1 EV3 Data2 A EV3 EV3 DataN ..... NA P EV3-1 EV4 7-bit Master receiver: S Address A EV5 Data1 A EV6 Data2 A EV7 EV7 DataN ..... NA P EV7 7-bit Master transmitter: S Address A EV5 Data1 A EV6 EV8 Data2 A EV8 DataN .....
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ST72325xx I2C BUS INTERFACE (Cont’d) 10.7.5 Low Power Modes Mode WAIT HALT Description No effect on I2C interface. I2C interrupts cause the device to exit from WAIT mode. I2C registers are frozen. In HALT mode, the I2C interface is inactive and does not acknowledge data on the bus. The I2C interface resumes operation when the MCU is woken up by an interrupt with “exit from HALT mode” capability. 10.7.6 Interrupts Figure 70.
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ST72325xx I2C BUS INTERFACE (Cont’d) 10.7.7 Register Description I2C CONTROL REGISTER (CR) Read / Write Reset Value: 0000 0000 (00h) – In slave mode: 0: No start generation 1: Start generation when the bus is free 7 0 0 0 PE ENGC START ACK STOP ITE Bit 2 = ACK Acknowledge enable. This bit is set and cleared by software. It is also cleared by hardware when the interface is disabled (PE=0).
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ST72325xx I2C BUS INTERFACE (Cont’d) I2C STATUS REGISTER 1 (SR1) Read Only Reset Value: 0000 0000 (00h) 1: Data byte transmitted 7 EVF 0 ADD10 TRA BUSY BTF ADSL M/SL SB Bit 7 = EVF Event flag. This bit is set by hardware as soon as an event occurs. It is cleared by software reading SR2 register in case of error event or as described in Figure 69. It is also cleared by hardware when the interface is disabled (PE=0).
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ST72325xx I2C BUS INTERFACE (Cont’d) Bit 1 = M/SL Master/Slave. This bit is set by hardware as soon as the interface is in Master mode (writing START=1). It is cleared by hardware after detecting a Stop condition on the bus or a loss of arbitration (ARLO=1). It is also cleared when the interface is disabled (PE=0). 0: Slave mode 1: Master mode Bit 0 = SB Start bit (Master mode). This bit is set by hardware as soon as the Start condition is generated (following a write START=1).
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ST72325xx I2C BUS INTERFACE (Cont’d) I2C CLOCK CONTROL REGISTER (CCR) Read / Write Reset Value: 0000 0000 (00h) 7 FM/SM CC6 CC5 CC4 CC3 CC2 CC1 I2C DATA REGISTER (DR) Read / Write Reset Value: 0000 0000 (00h) 0 7 CC0 D7 Bit 7 = FM/SM Fast/Standard I2C mode. This bit is set and cleared by software. It is not cleared when the interface is disabled (PE=0). 0: Standard I2C mode 1: Fast I2C mode Bit 6:0 = CC[6:0] 7-bit clock divider.
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ST72325xx I2C BUS INTERFACE (Cont’d) I2C OWN ADDRESS REGISTER (OAR1) Read / Write Reset Value: 0000 0000 (00h) 7 ADD7 ADD6 ADD5 ADD4 ADD3 ADD2 ADD1 I2C OWN ADDRESS REGISTER (OAR2) Read / Write Reset Value: 0100 0000 (40h) 0 7 ADD0 FR1 7-bit Addressing Mode Bit 7:1 = ADD[7:1] Interface address. These bits define the I2C bus address of the interface. They are not cleared when the interface is disabled (PE=0). 0 FR0 0 0 0 ADD9 ADD8 0 Bit 7:6 = FR[1:0] Frequency bits.
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ST72325xx I²C BUS INTERFACE (Cont’d) Table 25. I2C Register Map and Reset Values Address (Hex.
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ST72325xx 10.8 10-BIT A/D CONVERTER (ADC) 10.8.1 Introduction The on-chip Analog to Digital Converter (ADC) peripheral is a 10-bit, successive approximation converter with internal sample and hold circuitry. This peripheral has up to 16 multiplexed analog input channels (refer to device pin out description) that allow the peripheral to convert the analog voltage levels from up to 16 different sources. The result of the conversion is stored in a 10-bit Data Register.
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ST72325xx 10-BIT A/D CONVERTER (ADC) (Cont’d) 10.8.3 Functional Description The conversion is monotonic, meaning that the result never decreases if the analog input does not and never increases if the analog input does not. If the input voltage (VAIN) is greater than VAREF (high-level voltage reference) then the conversion result is FFh in the ADCDRH register and 03h in the ADCDRL register (without overflow indication).
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ST72325xx 10-BIT A/D CONVERTER (ADC) (Cont’d) 10.8.6 Register Description CONTROL/STATUS REGISTER (ADCCSR) Read/Write (Except bit 7 read only) Reset Value: 0000 0000 (00h) 7 EOC SPEED ADON Bit 3:0 = CH[3:0] Channel Selection These bits are set and cleared by software. They select the analog input to convert. 0 0 CH3 CH2 CH1 CH0 Bit 7 = EOC End of Conversion This bit is set by hardware. It is cleared by hardware when software reads the ADCDRH register or writes to any bit of the ADCCSR register.
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ST72325xx 10-BIT A/D CONVERTER (Cont’d) Table 26. ADC Register Map and Reset Values Address (Hex.
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ST72325xx 11 INSTRUCTION SET 11.
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ST72325xx INSTRUCTION SET OVERVIEW (Cont’d) 11.1.1 Inherent All Inherent instructions consist of a single byte. The opcode fully specifies all the required information for the CPU to process the operation.
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ST72325xx INSTRUCTION SET OVERVIEW (Cont’d) 11.1.6 Indirect Indexed (Short, Long) This is a combination of indirect and short indexed addressing modes. The operand is referenced by its memory address, which is defined by the unsigned addition of an index register value (X or Y) with a pointer value located in memory. The pointer address follows the opcode.
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ST72325xx INSTRUCTION SET OVERVIEW (Cont’d) 11.2 INSTRUCTION GROUPS The ST7 family devices use an Instruction Set consisting of 63 instructions.
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ST72325xx INSTRUCTION SET OVERVIEW (Cont’d) Mnemo Description Function/Example Dst Src I1 H I0 N Z C ADC Add with Carry A=A+M+C A M H N Z C ADD Addition A=A+M A M H N Z C AND Logical And A=A.M A M N Z BCP Bit compare A, Memory tst (A .
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ST72325xx INSTRUCTION SET OVERVIEW (Cont’d) Mnemo Description Function/Example Dst Src JRULE Jump if (C + Z = 1) Unsigned <= LD Load MUL dst <= src reg, M M, reg Multiply X,A = X * A A, X, Y X, Y, A NEG Negate (2's compl) neg $10 reg, M NOP No Operation OR OR operation A=A+M A M POP Pop from the Stack pop reg reg M pop CC CC M PUSH Push onto the Stack push Y M reg, CC RCF Reset carry flag C=0 RET Subroutine Return RIM Enable Interrupts I1:0 = 10 (level 0) R
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ST72325xx 12 ELECTRICAL CHARACTERISTICS 12.1 PARAMETER CONDITIONS Unless otherwise specified, all voltages are referred to VSS. 12.1.1 Minimum and Maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at TA=25°C and TA=TAmax (given by the selected temperature range).
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ST72325xx 12.2 ABSOLUTE MAXIMUM RATINGS Stresses above those listed as “absolute maximum ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device under these condi12.2.1 Voltage Characteristics Symbol tions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Ratings Maximum value VDD - VSS Supply voltage 6.
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ST72325xx 12.2.3 Thermal Characteristics Symbol TSTG TJ Ratings Storage temperature range Value Unit -65 to +150 °C Maximum junction temperature (see Section 13.2 THERMAL CHARACTERISTICS) 12.3 OPERATING CONDITIONS 12.3.1 General Operating Conditions Symbol Parameter Conditions fCPU Internal clock frequency VDD Standard voltage range (except Flash Write/Erase) Operating Voltage for Flash Write/Erase TA Ambient temperature range Min Max Unit 0 8 MHz 3.8 5.5 4.5 5.
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ST72325xx OPERATING CONDITIONS (Cont’d) 12.3.2 Operating Conditions with Low Voltage Detector (LVD) Subject to general operating conditions for VDD, fCPU, and TA. Symbol Parameter VIT+(LVD) Reset release threshold (VDD rise) VIT-(LVD) Reset generation threshold (VDD fall) Vhys(LVD) Conditions Min Typ Max VD level = High in option byte 4.01) 4.2 4.5 VD level = Med. in option byte2) 3.551) VD level = Low in option byte2) 2.951) 3.75 3.15 4.01) 3.351) VD level = High in option byte 4.0 4.
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ST72325xx 12.4 SUPPLY CURRENT CHARACTERISTICS The following current consumption specified for the ST7 functional operating modes over temperature range does not take into account the clock source current consumption. To get the total device consumption, the two current values must be added (except for HALT mode for which the clock is stopped). 12.4.1 CURRENT CONSUMPTION Symbol Parameter Conditions 2) Typ Max 1) 1.3 2.0 3.6 7.1 3.0 5.0 8.0 15.0 0.5 1.2 2.2 4.8 1.0 2.0 4.0 8.
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ST72325xx SUPPLY CURRENT CHARACTERISTICS (Cont’d) 12.4.2 Supply and Clock Managers The previous current consumption specified for the ST7 functional operating modes over temperature range does not take into account the clock source current consumption. To get the total device consumption, the two current values must be added (except for HALT mode). Symbol Parameter Conditions IDD(RCINT) Supply current of internal RC oscillator Typ Max Unit 625 see section 12.5.
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ST72325xx SUPPLY CURRENT CHARACTERISTICS (Cont’d) 12.4.3 On-Chip Peripherals Measured on LQFP64 generic board TA = 25°C fCPU=4MHz. Symbol Typ Unit IDD(TIM) 16-bit Timer supply current 1) Parameter Conditions VDD=5.0V 50 μA IDD(ART) ART PWM supply current2) VDD=5.0V 75 μA IDD(SPI) SPI supply current 3) VDD=5.0V 400 μA IDD(SCI) SCI supply current 4) VDD=5.0V 400 μA IDD(I2C) I2C supply current 5) VDD=5.0V 175 μA IDD(ADC) ADC supply current when converting 6) VDD=5.
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ST72325xx 12.5 CLOCK AND TIMING CHARACTERISTICS Subject to general operating conditions for VDD, fCPU, and TA. 12.5.1 General Timings Symbol tc(INST) tv(IT) Parameter Conditions Instruction cycle time Interrupt reaction time tv(IT) = Δtc(INST) + 10 fCPU=8MHz 2) fCPU=8MHz Min Typ 1) Max Unit 2 3 12 tCPU 250 375 1500 ns 10 22 tCPU 1.25 2.75 μs Max Unit 12.5.2 External Clock Source Symbol Parameter Conditions Min Typ VOSC1H OSC1 input pin high level voltage 0.
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ST72325xx CLOCK AND TIMING CHARACTERISTICS (Cont’d) 12.5.3 Crystal and Ceramic Resonator Oscillators The ST7 internal clock can be supplied with four different Crystal/Ceramic resonator oscillators. All the information given in this paragraph is based on characterization results with specified typical external components.
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ST72325xx Figure 76. Typical Application with a Crystal or Ceramic Resonator WHEN RESONATOR WITH INTEGRATED CAPACITORS CL1 fOSC POWER DOWN LOGIC OSC1 LINEAR AMPLIFIER RESONATOR RF CL2 VDD/2 Ref FEEDBACK LOOP i2 OSC2 ST72XXX 1. The relatively low value of the RF resistor, offers a good protection against issues resulting from use in a humid environment, due to the induced leakage and the bias condition change.
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ST72325xx CLOCK AND TIMING CHARACTERISTICS (Cont’d) Supplier fOSC (MHz) 2 Murata 4 8 16 Typical Ceramic Resonators2) CSTCC2M00G56Z-R0 SMD CSTCR4M00G53Z-R0 Lead CSTLS4M00G53Z-R0 SMD CSTCE8M00G52Z-R0 Lead CSTLS4M0052Z-R0 SMD CSTCE16M0V51Z-R0 Lead CSTLS16M0X51Z-R0 Notes: 1. Resonator characteristics given by the ceramic resonator manufacturer. 2.
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ST72325xx CLOCK CHARACTERISTICS (Cont’d) 12.5.4 RC Oscillators Symbol fOSC (RCINT) Parameter Conditions Internal RC oscillator frequency TA=25°C, VDD=5V See Figure 77 Figure 77. Typical fOSC(RCINT) vs TA Min Typ Max Unit 2 3.5 5.6 MHz Note: To reduce disturbance to the RC oscillator, it is recommended to place decoupling capacitors between VDD and VSS as shown in Figure 97 fOSC(RCINT) (MHz) 4 Vdd = 5V 3.8 Vdd = 5.5V 3.6 3.4 3.
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ST72325xx CLOCK CHARACTERISTICS (Cont’d) 12.5.5 Clock Security System (CSS) Symbol Parameter Conditions Min Safe Oscillator Frequency 1) fSFOSC Typ Max 3 Unit MHz Note: 1. Data based on characterization results. 12.5.6 PLL Characteristics Symbol Parameter Conditions PLL input frequency range fOSC Δ fCPU/ fCPU Instantaneous PLL jitter 1) Min Typ 2 fOSC = 4 MHz. 0.7 Max Unit 4 MHz 2 % Note: 1. Data characterized but not tested.
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ST72325xx 12.6 MEMORY CHARACTERISTICS 12.6.1 RAM and Hardware Registers Symbol VRM Parameter Data retention mode 1) Conditions HALT mode (or RESET) Min Typ Max 1.6 Unit V 12.6.
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ST72325xx 12.7 EMC CHARACTERISTICS Susceptibility tests are performed on a sample basis during product characterization. 12.7.1 Functional EMS (Electro Magnetic Susceptibility) Based on a simple running application on the product (toggling 2 LEDs through I/O ports), the product is stressed by two electro magnetic events until a failure occurs (indicated by the LEDs). ■ ESD: Electro-Static Discharge (positive and negative) is applied on all pins of the device until a functional disturbance occurs.
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ST72325xx EMC CHARACTERISTICS (Cont’d) 12.7.2 Electro Magnetic Interference (EMI) Based on a simple application running on the product (toggling 2 LEDs through the I/O ports), the product is monitored in terms of emission. This emission test is in line with the norm SAE J 1752/ 3 which specifies the board and the loading of each pin.
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ST72325xx EMC CHARACTERISTICS (Cont’d) 12.7.3 Absolute Maximum Ratings (Electrical Sensitivity) Based on two different tests (ESD and LU) using specific measurement methods, the product is stressed in order to determine its performance in terms of electrical sensitivity. For more details, refer to the application note AN1181. 12.7.3.
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ST72325xx 12.8 I/O PORT PIN CHARACTERISTICS 12.8.1 General Characteristics Subject to general operating conditions for VDD, fOSC, and TA unless otherwise specified. Symbol Parameter VIL Input low level voltage VIH Input high level voltage 1) Vhys IINJ(PIN)3) Conditions Min Typ 1) Schmitt trigger voltage hysteresis 0.7xVDD V 2) 0.
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ST72325xx I/O PORT PIN CHARACTERISTICS (Cont’d) 12.8.2 Output Driving Current Subject to general operating conditions for VDD, fCPU, and TA unless otherwise specified. Symbol Parameter Conditions VOL 1) Output low level voltage for a high sink I/O pin when 4 pins are sunk at same time (see Figure 82 and Figure 84) VDD=5V Output low level voltage for a standard I/O pin when 8 pins are sunk at same time (see Figure 81) Figure 81. Typical VOL at VDD=5V (standard) Max IIO=+5mA 1.2 IIO=+2mA 0.
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ST72325xx I/O PORT PIN CHARACTERISTICS (Cont’d) Figure 84. Typical VOL vs. VDD (standard) 1 0.45 Ta= -4 5°C 0.9 0.8 Ta=2 5°C Ta= 95°C Ta=9 5°C 0.35 Ta= 140 °C 0.7 Ta=1 40°C Vol(V) at Iio=2mA V ol(V ) at Iio=5m A Ta=-4 5°C 0.4 Ta= 25°C 0.6 0.5 0.4 0.3 0.3 0.25 0.2 0.15 0.2 0.1 0.1 0.05 0 2 2.5 3 3.5 4 4.5 5 5.5 0 6 2 Vdd(V ) 2.5 3 3.5 4 4.5 5 5.5 6 Vdd(V) Figure 85. Typical VOL vs. VDD (high-sink) 1 .6 0 .6 Ta = 140 °C 1 .4 0 .5 Ta =95 °C 1 .
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ST72325xx 12.9 CONTROL PIN CHARACTERISTICS 12.9.1 Asynchronous RESET Pin Subject to general operating conditions for VDD, fCPU, and TA unless otherwise specified. Symbol Parameter Conditions VIL Input low level voltage VIH Input high level voltage 1) Vhys Schmitt trigger voltage hysteresis 2) VOL Output low level voltage 3) IIO RON Min Typ 1) Filtered glitch duration 5) V IIO=+2mA 0.2 0.5 2 tw(RSTL)out Generated reset pulse duration tg(RSTL)in 0.3xVDD 2.
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ST72325xx CONTROL PIN CHARACTERISTICS (Cont’d) Figure 87. RESET pin protection when LVD is enabled.1)2)3)4) VDD Required Optional (note 3) ST72XXX RON EXTERNAL RESET INTERNAL RESET Filter 0.01μF 1MΩ PULSE GENERATOR WATCHDOG LVD RESET Figure 88. RESET pin protection when LVD is disabled.1) VDD ST72XXX RON USER EXTERNAL RESET CIRCUIT INTERNAL RESET Filter 0.01μF PULSE GENERATOR WATCHDOG Required Note 1: – The reset network protects the device against parasitic resets.
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ST72325xx CONTROL PIN CHARACTERISTICS (Cont’d) 12.9.2 ICCSEL/VPP Pin Subject to general operating conditions for VDD, fCPU, and TA unless otherwise specified. Symbol IL Parameter Input leakage current Conditions Min VIN=VSS Max1 Unit ±1 μA Figure 89. Two typical Applications with ICCSEL/VPP Pin 2) ICCSEL/VPP ST72XXX VPP PROGRAMMING TOOL 10kΩ Notes: 1. Data based on design simulation and/or technology characteristics, not tested in production. 2.
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ST72325xx 12.10 TIMER PERIPHERAL CHARACTERISTICS Subject to general operating conditions for VDD, fOSC, and TA unless otherwise specified. Refer to I/O port characteristics for more details on the input/output alternate function characteristics (output compare, input capture, external clock, PWM output...). 12.10.
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ST72325xx 12.11 COMMUNICATION INTERFACE CHARACTERISTICS 12.11.1 SPI - Serial Peripheral Interface Subject to general operating conditions for VDD, fCPU, and TA unless otherwise specified. Symbol fSCK 1/tc(SCK) tr(SCK) tf(SCK) Refer to I/O port characteristics for more details on the input/output alternate function characteristics (SS, SCK, MOSI, MISO). Parameter Conditions SPI clock frequency Min Max Master fCPU=8MHz fCPU/128 0.
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ST72325xx COMMUNICATION INTERFACE CHARACTERISTICS (Cont’d) Figure 91. SPI Slave Timing Diagram with CPHA=11) SS INPUT SCK INPUT tsu(SS) tc(SCK) th(SS) CPHA=1 CPOL=0 CPHA=1 CPOL=1 tw(SCKH) tw(SCKL) ta(SO) MISO OUTPUT see note 2 tv(SO) th(SO) MSB OUT HZ tsu(SI) BIT6 OUT LSB OUT tdis(SO) see note 2 th(SI) MSB IN MOSI INPUT tr(SCK) tf(SCK) BIT1 IN LSB IN Figure 92.
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ST72325xx COMMUNICATION INTERFACE CHARACTERISTICS (Cont’d) 12.11.2 I2C - Inter IC Control Interface Subject to general operating conditions for VDD, fCPU, and TA unless otherwise specified. Symbol Refer to I/O port characteristics for more details on the input/output alternate function characteristics (SDAI and SCLI). The ST7 I2C interface meets the requirements of the Standard I2C communication protocol described in the following table.
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ST72325xx COMMUNICATION INTERFACE CHARACTERISTICS (Cont’d) The following table gives the values to be written in the I2CCCR register to obtain the required I2C SCL line frequency. Table 29. SCL Frequency Table I2CCCR Value fSCL (kHz) 400 300 200 100 50 20 fCPU=4 MHz. VDD = 4.1 V RP=3.3kΩ RP=4.7kΩ NA NA NA NA 83h 83h 10h 10h 24h 24h 5Fh 5Fh VDD = 5 V RP=3.3kΩ RP=4.7kΩ NA NA NA NA 83h 83h 10h 10h 24h 24h 5Fh 5Fh fCPU=8 MHz. VDD = 4.1 V VDD = 5 V RP=3.3kΩ RP=4.7kΩ RP=3.3kΩ RP=4.
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ST72325xx 12.12 10-BIT ADC CHARACTERISTICS Subject to general operating conditions for VDD, fCPU, and TA unless otherwise specified. Symbol fADC VAREF VAIN Parameter Conditions ADC clock frequency 0.7*VDD ≤ VAREF ≤ VDD Analog reference voltage Conversion voltage range 1) Min Max Unit 0.4 Typ 2 MHz 3.
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ST72325xx ADC CHARACTERISTICS (Cont’d) Figure 94. RAIN max. vs fADC with CAIN=0pF1) Figure 95. Recommended CAIN & RAIN values.2) 45 1000 Cain 10 nF 2 MHz 35 30 1 MHz 25 Cain 22 nF 100 Max. R AIN (Kohm) Max. R AIN (Kohm) 40 20 15 10 Cain 47 nF 10 1 5 0 0.1 0 10 30 70 0.01 0.1 CPARASITIC (pF) 1 10 fAIN(KHz) Figure 96. Typical A/D Converter Application VDD RAIN AINx ST72XXX VT 0.6V 2kΩ(max) VAIN CAIN VT 0.6V IL ±1μA 10-Bit A/D Conversion CADC 12pF Notes: 1.
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ST72325xx ADC CHARACTERISTICS (Cont’d) 12.12.1 Analog Power Supply and Reference Pins Depending on the MCU pin count, the package may feature separate VAREF and VSSA analog power supply pins. These pins supply power to the A/D converter cell and function as the high and low reference voltages for the conversion. Separation of the digital and analog power pins allow board designers to improve A/D performance.
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ST72325xx 10-BIT ADC CHARACTERISTICS (Cont’d) 12.12.3 ADC Accuracy Conditions: VDD=5V 1) Symbol |ET| |EO| |EG| Typ Max2) 3 4 2 3 0.5 3 CPU in run mode @ fADC 2 MHz. 1 2 CPU in run mode @ fADC 2 MHz. 1 2 Parameter Total unadjusted error Offset error Gain Error Conditions 1) 1) 1) |ED| Differential linearity error |EL| Integral linearity error 1) 1) Unit LSB Notes: 1. ADC Accuracy vs.
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ST72325xx 13 PACKAGE CHARACTERISTICS 13.1 PACKAGE MECHANICAL DATA Figure 99. 64-Pin Low Profile Quad Flat Package (14x14) D A D1 A2 b e E1 E L Min Typ c h Max Min Typ Max 1.60 0.0630 0.15 0.0020 0.0059 A1 0.05 A2 1.35 1.40 1.45 0.0531 0.0551 0.0571 b 0.30 0.37 0.45 0.0118 0.0146 0.0177 c 0.09 0.20 0.0035 0.0079 D 16.00 0.6299 D1 14.00 0.5512 E 16.00 0.6299 E1 14.00 0.5512 e 0.80 0.0315 θ 0° 3.5° L 0.45 0.60 L1 L1 inches1) mm A A1 174/197 Dim. 1.
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ST72325xx Figure 100. 64-Pin Low Profile Quad Flat Package (10 x10) Dim. D A D1 A2 b E1 E e c L1 θ L Min Typ A A1 inches1) mm Max Min Typ Max 1.60 0.0630 0.15 0.0020 0.0059 A1 0.05 A2 1.35 1.40 1.45 0.0531 0.0551 0.0571 b 0.17 0.22 0.27 0.0067 0.0087 0.0106 c 0.09 0.20 0.0035 0.0079 D 12.00 0.4724 D1 10.00 0.3937 E 12.00 0.4724 E1 10.00 0.3937 e 0.50 θ 0° 3.5° L 0.45 0.60 L1 0.0197 7° 0° 3.5° 7° 0.75 0.0177 0.0236 0.0295 1.00 0.
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ST72325xx Figure 102. 44-Pin Low Profile Quad Flat Package Dim. A A2 D D1 b e E1 E c L1 L h Min Typ A A1 inches1) mm Max Min Typ Max 1.60 0.0630 0.15 0.0020 0.0059 A1 0.05 A2 1.35 1.40 1.45 0.0531 0.0551 0.0571 b 0.30 0.37 0.45 0.0118 0.0146 0.0177 C 0.09 0.20 0.0035 0.0079 D 12.00 0.4724 D1 10.00 0.3937 E 12.00 0.4724 E1 10.00 0.3937 e 0.80 θ 0° 3.5° L 0.45 0.60 L1 1.00 0.0315 7° 0° 3.5° 7° 0.75 0.0177 0.0236 0.0295 0.
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ST72325xx PACKAGE MECHANICAL DATA (Cont’d) Figure 103. 42-Pin Plastic Dual In-Line Package, Shrink 600-mil Width Dim. A2 A1 b2 b A L c e eB Typ 5.08 Max 0.2000 0.51 3.05 3.81 4.57 0.1201 0.1500 0.1799 0.0201 b 0.38 0.46 0.56 0.0150 0.0181 0.0220 b2 0.89 1.02 1.14 0.0350 0.0402 0.0449 c 0.23 0.25 0.38 0.0091 0.0098 0.0150 D 36.58 36.83 37.08 1.4402 1.4500 1.4598 E 15.24 E1 12.70 13.72 14.48 0.5000 0.5402 0.5701 0.
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ST72325xx PACKAGE MECHANICAL DATA (Cont’d) Figure 105. 32-Pin Low Profile Quad Flat Package Dim. Min Typ D A A D1 A2 A1 0.05 A2 1.35 1.40 b 0.30 0.37 C 0.09 A1 e E1 E b c L1 L h inches1) mm Max Min Typ 1.60 0.0630 0.15 0.0020 0.0059 1.45 0.0531 0.0551 0.0571 0.45 0.0118 0.0146 0.0177 0.20 0.0035 0.0079 D 9.00 0.3543 D1 7.00 0.2756 E 9.00 0.3543 E1 7.00 0.2756 e 0.80 θ 0° 3.5° L 0.45 0.60 L1 1.00 Max 0.0315 7° 0° 3.5° 7° 0.75 0.0177 0.0236 0.
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ST72325xx 13.2 THERMAL CHARACTERISTICS Symbol Ratings Value RthJA Package thermal resistance (junction to ambient) LQFP64 10x10 LQFP48 7x7 LQFP44 10x10 SDIP42 LQFP32 7x7 SDIP32 50 80 52 55 70 50 PD TJmax Unit °C/W Power dissipation 1) 500 mW Maximum junction temperature 2) 150 °C Notes: 1. The maximum chip-junction temperature is based on technology characteristics. 2. The maximum power dissipation is obtained from the formula PD = (TJ -TA) / RthJA.
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ST72325xx 13.3 SOLDERING INFORMATION ■ In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a lead-free second level interconnect. The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The 180/197 ■ maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK® specifications are available at www.st.
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ST72325xx 14 ST72325 DEVICE CONFIGURATION AND ORDERING INFORMATION Each device is available for production in user programmable versions (FLASH) as well as in factory coded versions (ROM/FASTROM). ST72325 devices are ROM versions. ST72P325 devices are Factory Advanced Service Technique ROM (FASTROM) versions: they are factory-programmed HDFlash devices. FLASH devices are shipped to customers with a default content, while ROM/FASTROM factory coded parts contain the code supplied by the customer.
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ST72325xx ST72325 DEVICE CONFIGURATION AND ORDERING INFORMATION (Cont’d) OPT0= FMP_R Flash memory read-out protection Read-out protection, when selected, provides a protection against Program Memory content extraction and against write access to Flash memory. Erasing the option bytes when the FMP_R option is selected causes the whole user memory to be erased first, and the device can be reprogrammed. Refer to Section 4.3.1 and the ST7 Flash Programming Reference Manual for more details.
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ST72325xx ST72325 DEVICE CONFIGURATION AND ORDERING INFORMATION (Cont’d) 14.2 DEVICE ORDERING INFORMATION AND TRANSFER OF CUSTOMER CODE Customer code is made up of the ROM/FASTROM contents and the list of the selected options (if any). The ROM/FASTROM contents are to be sent on diskette, or by electronic means, with the S19 hexadecimal file generated by the development tool. All unused bytes must be set to FFh.
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ST72325xx Figure 106. Ordering information scheme Example: ST72 F 325 K 6 T 6 Family ST7 microcontroller family Memory type F: Flash Blank : ROM P = FASTROM Sub-family 325 No. of pins K = 32 J = 44 or 42 S or C = 48 AR = 64 (LQFP64 10x10 package) R = 64 (LQFP64 14x14 package) Memory size 4 = 16K 6 = 32K 7 = 48K 9 = 60K Package T = LQFP B = DIP Temperature range 6 = -40 °C to 85 °C 3 = -40 °C to 125 °C For a list of available options (e.g.
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ST72325xx ST72325 DEVICE CONFIGURATION AND ORDERING INFORMATION (Cont’d) ST72325 ROM MICROCONTROLLER OPTION LIST (Last update: October 2008) Customer: ........................................................................ Address: ........................................................................ ........................................................................ Contact: ........................................................................ Phone No: ........................................
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ST72325xx DEVICE CONFIGURATION AND ORDERING INFORMATION (Cont’d) ST72P325 FASTROM MICROCONTROLLER OPTION LIST (Last update: October 2008) Customer: ........................................................................ Address: ........................................................................ ........................................................................ Contact: ........................................................................ Phone No: ...........................................
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ST72325xx 14.3 DEVELOPMENT TOOLS Development tools for the ST7 microcontrollers include a complete range of hardware systems and software tools from STMicroelectronics and thirdparty tool suppliers. The range of tools includes solutions to help you evaluate microcontroller peripherals, develop and debug your application, and program your microcontrollers. 14.3.1 Starter kits ST offers complete, affordable starter kits.
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ST72325xx DEVICE CONFIGURATION AND ORDERING INFORMATION (Cont’d) Table 31. Suggested List of Socket Types Device Socket Emulator Adapter LQFP64 14 x14 CAB 3303262 CAB 3303351 LQFP64 10 x10 YAMAICHI IC149-064-*75-*5 YAMAICHI ICP-064-6 LQFP48 7 X7 CAB 3303238 CAB 3303333 LQFP44 10 X10 YAMAICHI IC149-044-*52-*5 YAMAICHI ICP-044-5 LQFP32 7 X 7 IRONWOOD SF-QFE32SA-L-01 IRONWOOD SK-UGA06/32A-01 14.3.
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ST72325xx 14.4 ST7 APPLICATION NOTES Table 32.
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ST72325xx Table 32.
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ST72325xx Table 32.
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ST72325xx 15 KNOWN LIMITATIONS 15.1 ALL DEVICES 15.1.1 Unexpected Reset Fetch If an interrupt request occurs while a “POP CC” instruction is executed, the interrupt controller does not recognise the source of the interrupt and, by default, passes the RESET vector address to the CPU. Workaround To solve this issue, a “POP CC” instruction must always be preceded by a “SIM” instruction. 15.1.
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ST72325xx LD sema,A IRET Case 2: Writing to PxOR or PxDDR with Global Interrupts Disabled: SIM ; set the interrupt mask LD A,PFDR AND A,#$02 LD X,A ; store the level before writing to PxOR/PxDDR LD A,#$90 LD PFDDR,A; Write into PFDDR LD A,#$ff LD PFOR,A ; Write to PFOR LD A,PFDR AND A,#$02 LD Y,A ; store the level after writing to PxOR/ PxDDR LD A,X ; check for falling edge cp A,#$02 jrne OUT TNZ Y jrne OUT LD A,#$01 LD sema,A ; set the semaphore to '1' if edge is detected RIM ; reset the interrupt mask LD
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ST72325xx KNOWN LIMITATIONS (Cont’d) 15.1.4 SCI Wrong Break duration Description A single break character is sent by setting and resetting the SBK bit in the SCICR2 register. In some cases, the break character may have a longer duration than expected: - 20 bits instead of 10 bits if M=0 - 22 bits instead of 11 bits if M=1. In the same way, as long as the SBK bit is set, break characters are sent to the TDO pin. This may lead to generate one break more than expected.
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ST72325xx KNOWN LIMITATIONS (Cont’d) 15.1.8 Pull-up always active on PE2 The I/O port internal pull-up is always active on I/O port E2. As a result, if PE2 is in output mode low level, current consumption in Halt/Active Halt mode is increased. 15.1.9 ADC accuracy 16/32K Flash devices The ADC accuracy in 16/32K Flash Devices deviates from table in section 12.12.3 on page 173 as follows: Symbol Max |ET| 6 |EO| 5 |EG| 4.
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ST72325xx 16 REVISION HISTORY Table 33. Revision History Date Revision 26-Sep-2005 1 Description of Changes Initial release Modified LQFP48 pinout, added S device ordering information Modified Note 4 on page 16 for unbonded pins in 48 pin C devices Added caution about reset vector in unprogrammed Flash devices in Section 6.3. 04-Dec-2006 2 Removed EMC protective circuitry in Figure 88 on page 163 (device works correctly without these components) Modified SS min.
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