Specifications
Table Of Contents
- Contents
- List of tables
- List of figures
- 1 Description
- 2 Register and memory map
- 3 Flash program memory
- 4 Central processing unit
- 5 Supply, reset and clock management
- 6 Interrupts
- 7 Power saving modes
- 8 I/O ports
- 9 Window watchdog (WWDG)
- 10 Main clock controller with real time clock MCC/RTC
- 11 PWM auto-reload timer (ART)
- 11.1 Introduction
- 11.2 Functional description
- 11.2.1 Counter
- 11.2.2 Counter clock and prescaler
- 11.2.3 Counter and prescaler Initialization
- 11.2.4 Output compare control
- 11.2.5 Independent PWM signal generation
- 11.2.6 Output compare and Time base interrupt
- 11.2.7 External clock and event detector mode
- 11.2.8 Input capture function
- 11.2.9 External interrupt capability
- 11.3 Register description
- 12 16-bit timer
- 12.1 Introduction
- 12.2 Main features
- 12.3 Functional description
- 12.4 Low power modes
- 12.5 Interrupts
- 12.6 Summary of timer modes
- 12.7 Register description
- 12.7.1 Control register 1 (CR1)
- 12.7.2 Control register 2 (CR2)
- 12.7.3 Control/status register (CSR)
- 12.7.4 Input capture 1 high register (IC1HR)
- 12.7.5 Input capture 1 low register (IC1LR)
- 12.7.6 Output compare 1 high register (OC1HR)
- 12.7.7 Output compare 1 low register (OC1LR)
- 12.7.8 Output compare 2 high register (OC2HR)
- 12.7.9 Output compare 2 low register (OC2LR)
- 12.7.10 Counter high register (CHR)
- 12.7.11 Counter low register (CLR)
- 12.7.12 Alternate counter high register (ACHR)
- 12.7.13 Alternate counter low register (ACLR)
- 12.7.14 Input capture 2 high register (IC2HR)
- 12.7.15 Input capture 2 low register (IC2LR)
- 13 8-bit timer (TIM8)
- 13.1 Introduction
- 13.2 Main features
- 13.3 Functional description
- 13.4 Low power modes
- 13.5 Interrupts
- 13.6 Summary of timer modes
- 13.7 Register description
- 13.7.1 Control register 1 (CR1)
- 13.7.2 Control register 2 (CR2)
- 13.7.3 Control/status register (CSR)
- 13.7.4 Input capture 1 register (IC1R)
- 13.7.5 Output compare 1 register (OC1R)
- 13.7.6 Output compare 2 register (OC2R)
- 13.7.7 Counter register (CTR)
- 13.7.8 Alternate counter register (ACTR)
- 13.7.9 Input capture 2 register (IC2R)
- 13.8 8-bit timer register map
- 14 Serial peripheral interface (SPI)
- 15 LINSCI serial communication interface (LIN master/slave)
- 15.1 Introduction
- 15.2 SCI features
- 15.3 LIN features
- 15.4 General description
- 15.5 SCI mode - functional description
- 15.6 Low power modes
- 15.7 Interrupts
- 15.8 SCI mode register description
- 15.9 LIN mode - functional description.
- 15.9.1 Entering LIN mode
- 15.9.2 LIN transmission
- 15.9.3 LIN reception
- 15.9.4 LIN error detection
- 15.9.5 LIN baud rate
- 15.9.6 LIN slave baud rate generation
- 15.9.7 LINSCI clock tolerance
- 15.9.8 Clock deviation causes
- 15.9.9 Error due to LIN synch measurement
- 15.9.10 Error due to baud rate quantization
- 15.9.11 Impact of clock deviation on maximum baud rate
- 15.10 LIN mode register description
- 16 LINSCI serial communication interface (LIN master only)
- 16.1 Introduction
- 16.2 Main features
- 16.3 General description
- 16.4 Functional description
- 16.5 Low power modes
- 16.6 Interrupts
- 16.7 SCI synchronous transmission
- 16.8 Register description
- 16.8.1 Status register (SCISR)
- 16.8.2 Control register 1 (SCICR1)
- 16.8.3 Control register 2 (SCICR2)
- 16.8.4 Control Register 3 (SCICR3)
- 16.8.5 Data register (SCIDR)
- 16.8.6 Baud rate register (SCIBRR)
- 16.8.7 Extended receive prescaler division register (SCIERPR)
- 16.8.8 Extended transmit prescaler division register (SCIETPR)
- 17 10-bit A/D converter (ADC)
- 18 Instruction set
- 19 Electrical characteristics
- 19.1 Parameter conditions
- 19.2 Absolute maximum ratings
- 19.3 Operating conditions
- 19.4 Supply current characteristics
- 19.5 Clock and timing characteristics
- 19.6 Auto wakeup from halt oscillator (AWU)
- 19.7 Memory characteristics
- 19.8 EMC characteristics
- 19.9 I/O port pin characteristics
- 19.10 Control pin characteristics
- 19.11 Timer peripheral characteristics
- 19.12 Communication interface characteristics
- 19.13 10-bit ADC characteristics
- 20 Package characteristics
- 21 Device configuration and ordering information
- 22 Development tools
- 23 Important notes
- 24 Revision history
ST72361xx-Auto Contents
Doc ID 12468 Rev 3 9/279
16.4.2 Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
16.4.3 Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
16.4.4 Conventional baud rate generation . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
16.4.5 Extended baud rate generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
16.4.6 Receiver muting and wake-up feature . . . . . . . . . . . . . . . . . . . . . . . . . 201
16.4.7 Parity control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
16.5 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
16.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
16.7 SCI synchronous transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
16.8 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
16.8.1 Status register (SCISR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
16.8.2 Control register 1 (SCICR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
16.8.3 Control register 2 (SCICR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
16.8.4 Control Register 3 (SCICR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
16.8.5 Data register (SCIDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
16.8.6 Baud rate register (SCIBRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
16.8.7 Extended receive prescaler division register (SCIERPR) . . . . . . . . . . 212
16.8.8 Extended transmit prescaler division register (SCIETPR) . . . . . . . . . . 212
17 10-bit A/D converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
17.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
17.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
17.3 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
17.3.1 Digital A/D conversion result . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
17.3.2 A/D conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
17.3.3 Changing the conversion channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
17.3.4 ADCDR consistency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
17.4 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
17.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
17.6 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
17.6.1 Control/status register (ADCCSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
17.6.2 Data register (ADCDRH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
17.6.3 Data register (ADCDRL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
18 Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
18.1 CPU addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219