Specifications
Table Of Contents
- Contents
- List of tables
- List of figures
- 1 Description
- 2 Register and memory map
- 3 Flash program memory
- 4 Central processing unit
- 5 Supply, reset and clock management
- 6 Interrupts
- 7 Power saving modes
- 8 I/O ports
- 9 Window watchdog (WWDG)
- 10 Main clock controller with real time clock MCC/RTC
- 11 PWM auto-reload timer (ART)
- 11.1 Introduction
- 11.2 Functional description
- 11.2.1 Counter
- 11.2.2 Counter clock and prescaler
- 11.2.3 Counter and prescaler Initialization
- 11.2.4 Output compare control
- 11.2.5 Independent PWM signal generation
- 11.2.6 Output compare and Time base interrupt
- 11.2.7 External clock and event detector mode
- 11.2.8 Input capture function
- 11.2.9 External interrupt capability
- 11.3 Register description
- 12 16-bit timer
- 12.1 Introduction
- 12.2 Main features
- 12.3 Functional description
- 12.4 Low power modes
- 12.5 Interrupts
- 12.6 Summary of timer modes
- 12.7 Register description
- 12.7.1 Control register 1 (CR1)
- 12.7.2 Control register 2 (CR2)
- 12.7.3 Control/status register (CSR)
- 12.7.4 Input capture 1 high register (IC1HR)
- 12.7.5 Input capture 1 low register (IC1LR)
- 12.7.6 Output compare 1 high register (OC1HR)
- 12.7.7 Output compare 1 low register (OC1LR)
- 12.7.8 Output compare 2 high register (OC2HR)
- 12.7.9 Output compare 2 low register (OC2LR)
- 12.7.10 Counter high register (CHR)
- 12.7.11 Counter low register (CLR)
- 12.7.12 Alternate counter high register (ACHR)
- 12.7.13 Alternate counter low register (ACLR)
- 12.7.14 Input capture 2 high register (IC2HR)
- 12.7.15 Input capture 2 low register (IC2LR)
- 13 8-bit timer (TIM8)
- 13.1 Introduction
- 13.2 Main features
- 13.3 Functional description
- 13.4 Low power modes
- 13.5 Interrupts
- 13.6 Summary of timer modes
- 13.7 Register description
- 13.7.1 Control register 1 (CR1)
- 13.7.2 Control register 2 (CR2)
- 13.7.3 Control/status register (CSR)
- 13.7.4 Input capture 1 register (IC1R)
- 13.7.5 Output compare 1 register (OC1R)
- 13.7.6 Output compare 2 register (OC2R)
- 13.7.7 Counter register (CTR)
- 13.7.8 Alternate counter register (ACTR)
- 13.7.9 Input capture 2 register (IC2R)
- 13.8 8-bit timer register map
- 14 Serial peripheral interface (SPI)
- 15 LINSCI serial communication interface (LIN master/slave)
- 15.1 Introduction
- 15.2 SCI features
- 15.3 LIN features
- 15.4 General description
- 15.5 SCI mode - functional description
- 15.6 Low power modes
- 15.7 Interrupts
- 15.8 SCI mode register description
- 15.9 LIN mode - functional description.
- 15.9.1 Entering LIN mode
- 15.9.2 LIN transmission
- 15.9.3 LIN reception
- 15.9.4 LIN error detection
- 15.9.5 LIN baud rate
- 15.9.6 LIN slave baud rate generation
- 15.9.7 LINSCI clock tolerance
- 15.9.8 Clock deviation causes
- 15.9.9 Error due to LIN synch measurement
- 15.9.10 Error due to baud rate quantization
- 15.9.11 Impact of clock deviation on maximum baud rate
- 15.10 LIN mode register description
- 16 LINSCI serial communication interface (LIN master only)
- 16.1 Introduction
- 16.2 Main features
- 16.3 General description
- 16.4 Functional description
- 16.5 Low power modes
- 16.6 Interrupts
- 16.7 SCI synchronous transmission
- 16.8 Register description
- 16.8.1 Status register (SCISR)
- 16.8.2 Control register 1 (SCICR1)
- 16.8.3 Control register 2 (SCICR2)
- 16.8.4 Control Register 3 (SCICR3)
- 16.8.5 Data register (SCIDR)
- 16.8.6 Baud rate register (SCIBRR)
- 16.8.7 Extended receive prescaler division register (SCIERPR)
- 16.8.8 Extended transmit prescaler division register (SCIETPR)
- 17 10-bit A/D converter (ADC)
- 18 Instruction set
- 19 Electrical characteristics
- 19.1 Parameter conditions
- 19.2 Absolute maximum ratings
- 19.3 Operating conditions
- 19.4 Supply current characteristics
- 19.5 Clock and timing characteristics
- 19.6 Auto wakeup from halt oscillator (AWU)
- 19.7 Memory characteristics
- 19.8 EMC characteristics
- 19.9 I/O port pin characteristics
- 19.10 Control pin characteristics
- 19.11 Timer peripheral characteristics
- 19.12 Communication interface characteristics
- 19.13 10-bit ADC characteristics
- 20 Package characteristics
- 21 Device configuration and ordering information
- 22 Development tools
- 23 Important notes
- 24 Revision history
ST72361xx-Auto Electrical characteristics
Doc ID 12468 Rev 3 231/279
19.3.3 Auxiliary voltage detector (AVD) thresholds
Subject to general operating conditions for T
A
.
Figure 98. LVD startup behavior
Note: When the LVD is enabled, the MCU reaches its authorized operating voltage from a reset
state. However, in some devices, the reset signal may be undefined until V
DD
is
approximately 2V. As a consequence, the I/Os may toggle when V
DD
is below this voltage.
Because Flash write access is impossible below this voltage, the Flash memory contents
will not be corrupted.
19.4 Supply current characteristics
The following current consumption specified for the ST7 functional operating modes over
temperature range does not take into account the clock source current consumption. To get
the total device consumption, the two current values must be added (except for HALT mode
for which the clock is stopped).
Symbol Parameter Conditions Min Typ Max Unit
V
IT+(AVD)
10 AVDF flag toggle
threshold (V
DD
rise)
4.4
(1)
1. Data based on characterization results, not tested in production.
4.6 4.9
V
V
IT-(AVD)
01 AVDF flag toggle
threshold (V
DD
fall)
4.2 4.4 4.65
(1)
V
hys(AVD)
AVD voltage threshold
hysteresis
V
IT+(AVD)
-V
IT-(AVD)
250
mV
V
IT-
Voltage drop between AVD
flag set and LVD reset
activated
V
IT-(AVD)
-V
IT-(LVD)
450
5V
2V
V
IT+
LVD RESET
V
D
D
t
Reset state
in this area
not defined