Specifications
Table Of Contents
- Contents
- List of tables
- List of figures
- 1 Description
- 2 Register and memory map
- 3 Flash program memory
- 4 Central processing unit
- 5 Supply, reset and clock management
- 6 Interrupts
- 7 Power saving modes
- 8 I/O ports
- 9 Window watchdog (WWDG)
- 10 Main clock controller with real time clock MCC/RTC
- 11 PWM auto-reload timer (ART)
- 11.1 Introduction
- 11.2 Functional description
- 11.2.1 Counter
- 11.2.2 Counter clock and prescaler
- 11.2.3 Counter and prescaler Initialization
- 11.2.4 Output compare control
- 11.2.5 Independent PWM signal generation
- 11.2.6 Output compare and Time base interrupt
- 11.2.7 External clock and event detector mode
- 11.2.8 Input capture function
- 11.2.9 External interrupt capability
- 11.3 Register description
- 12 16-bit timer
- 12.1 Introduction
- 12.2 Main features
- 12.3 Functional description
- 12.4 Low power modes
- 12.5 Interrupts
- 12.6 Summary of timer modes
- 12.7 Register description
- 12.7.1 Control register 1 (CR1)
- 12.7.2 Control register 2 (CR2)
- 12.7.3 Control/status register (CSR)
- 12.7.4 Input capture 1 high register (IC1HR)
- 12.7.5 Input capture 1 low register (IC1LR)
- 12.7.6 Output compare 1 high register (OC1HR)
- 12.7.7 Output compare 1 low register (OC1LR)
- 12.7.8 Output compare 2 high register (OC2HR)
- 12.7.9 Output compare 2 low register (OC2LR)
- 12.7.10 Counter high register (CHR)
- 12.7.11 Counter low register (CLR)
- 12.7.12 Alternate counter high register (ACHR)
- 12.7.13 Alternate counter low register (ACLR)
- 12.7.14 Input capture 2 high register (IC2HR)
- 12.7.15 Input capture 2 low register (IC2LR)
- 13 8-bit timer (TIM8)
- 13.1 Introduction
- 13.2 Main features
- 13.3 Functional description
- 13.4 Low power modes
- 13.5 Interrupts
- 13.6 Summary of timer modes
- 13.7 Register description
- 13.7.1 Control register 1 (CR1)
- 13.7.2 Control register 2 (CR2)
- 13.7.3 Control/status register (CSR)
- 13.7.4 Input capture 1 register (IC1R)
- 13.7.5 Output compare 1 register (OC1R)
- 13.7.6 Output compare 2 register (OC2R)
- 13.7.7 Counter register (CTR)
- 13.7.8 Alternate counter register (ACTR)
- 13.7.9 Input capture 2 register (IC2R)
- 13.8 8-bit timer register map
- 14 Serial peripheral interface (SPI)
- 15 LINSCI serial communication interface (LIN master/slave)
- 15.1 Introduction
- 15.2 SCI features
- 15.3 LIN features
- 15.4 General description
- 15.5 SCI mode - functional description
- 15.6 Low power modes
- 15.7 Interrupts
- 15.8 SCI mode register description
- 15.9 LIN mode - functional description.
- 15.9.1 Entering LIN mode
- 15.9.2 LIN transmission
- 15.9.3 LIN reception
- 15.9.4 LIN error detection
- 15.9.5 LIN baud rate
- 15.9.6 LIN slave baud rate generation
- 15.9.7 LINSCI clock tolerance
- 15.9.8 Clock deviation causes
- 15.9.9 Error due to LIN synch measurement
- 15.9.10 Error due to baud rate quantization
- 15.9.11 Impact of clock deviation on maximum baud rate
- 15.10 LIN mode register description
- 16 LINSCI serial communication interface (LIN master only)
- 16.1 Introduction
- 16.2 Main features
- 16.3 General description
- 16.4 Functional description
- 16.5 Low power modes
- 16.6 Interrupts
- 16.7 SCI synchronous transmission
- 16.8 Register description
- 16.8.1 Status register (SCISR)
- 16.8.2 Control register 1 (SCICR1)
- 16.8.3 Control register 2 (SCICR2)
- 16.8.4 Control Register 3 (SCICR3)
- 16.8.5 Data register (SCIDR)
- 16.8.6 Baud rate register (SCIBRR)
- 16.8.7 Extended receive prescaler division register (SCIERPR)
- 16.8.8 Extended transmit prescaler division register (SCIETPR)
- 17 10-bit A/D converter (ADC)
- 18 Instruction set
- 19 Electrical characteristics
- 19.1 Parameter conditions
- 19.2 Absolute maximum ratings
- 19.3 Operating conditions
- 19.4 Supply current characteristics
- 19.5 Clock and timing characteristics
- 19.6 Auto wakeup from halt oscillator (AWU)
- 19.7 Memory characteristics
- 19.8 EMC characteristics
- 19.9 I/O port pin characteristics
- 19.10 Control pin characteristics
- 19.11 Timer peripheral characteristics
- 19.12 Communication interface characteristics
- 19.13 10-bit ADC characteristics
- 20 Package characteristics
- 21 Device configuration and ordering information
- 22 Development tools
- 23 Important notes
- 24 Revision history
ST72361xx-Auto LINSCI serial communication interface (LIN master/slave)
Doc ID 12468 Rev 3 187/279
Bit 4 = LASE LIN Auto Synch Enable.
This bit enables the Auto Synch Unit (ASU). It is set and cleared by software. It is only
usable in LIN Slave mode.
0: auto synch unit disabled
1: auto synch unit enabled.
Bit 3 = LHDM LIN Header Detection Method
This bit is set and cleared by software. It is only usable in LIN Slave mode. It enables the
Header Detection Method. In addition if the RWU bit in the
SCICR2 register is set, the LHDM bit selects the Wake-Up method (replacing the WAKE bit).
0: LIN synch break detection method
1: LIN Identifier field detection method
Bit 2 = LHIE LIN Header Interrupt Enable
This bit is set and cleared by software. It is only usable in LIN Slave mode.
0: LIN header interrupt is inhibited.
1: An SCI interrupt is generated whenever LHDF = 1.
Bit 1 = LHDF LIN Header Detection Flag
This bit is set by hardware when a LIN Header is detected and cleared by a software
sequence (an access to the SCISR register followed by a read of the SCICR3 register). It is
only usable in LIN slave mode.
0: no LIN header detected.
1: LIN header detected.
Note: The header detection method depends on the LHDM bit:
- If LHDM = 0, a header is detected as a LIN synch break.
- If LHDM = 1, a header is detected as a LIN Identifier, meaning that a LIN synch
break field + a LIN synch field + a LIN identifier field have been consecutively received.
Bit 0 = LSF LIN Synch Field State
This bit indicates that the LIN synch field is being analyzed. It is only used in LIN slave
mode. In auto synchronization mode (LASE bit = 1), when the SCI is in the LIN synch field
State it waits or counts the falling edges on the RDI line.
It is set by hardware as soon as a LIN synch break is detected and cleared by hardware
when the LIN synch field analysis is finished (see Figure 87). This bit can also be cleared by
software to exit LIN synch state and return to idle mode.
0: the current character is not the LIN synch field
1: LIN synch field state (LIN synch field undergoing analysis)
Figure 87. LSF bit set and clear
LIN Synch LIN Synch Identifier
parity bits
Field
Field
Break
11 dominant bits
LSF bit