ST72361xx-Auto 8-bit MCU for automotive with Flash or ROM, 10-bit ADC, 5 timers, SPI, LINSCI™ Features ■ ■ ■ Memories – 16 K to 60 K High Density Flash (HDFlash) or ROM with read-out protection capability. In-application programming and in-circuit programming for HDFlash devices – 1.
Contents ST72361xx-Auto Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 1.1 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2 Register and memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3 Flash program memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.1 Introduction . . . . . . . . . . . . . .
ST72361xx-Auto 5.6 6 5.5.2 Asynchronous external RESET pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 5.5.3 External power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 5.5.4 Internal low voltage detector (LVD) reset . . . . . . . . . . . . . . . . . . . . . . . . 42 5.5.5 Internal watchdog reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 System integrity management (SI) . . . . . . . . . . . . . . . . . . .
Contents 9 10 ST72361xx-Auto 8.2.2 Output modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 8.2.3 Alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 8.3 I/O port implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 8.4 I/O port register configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 8.4.1 Standard ports . . . . . . . . .
ST72361xx-Auto Contents 11.2 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 11.3 12 11.2.1 Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 11.2.2 Counter clock and prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 11.2.3 Counter and prescaler Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 11.2.4 Output compare control . . .
Contents ST72361xx-Auto 12.7.8 Output compare 2 high register (OC2HR) . . . . . . . . . . . . . . . . . . . . . . 120 12.7.9 Output compare 2 low register (OC2LR) . . . . . . . . . . . . . . . . . . . . . . . 121 12.7.10 Counter high register (CHR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 12.7.11 Counter low register (CLR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 12.7.12 Alternate counter high register (ACHR) . . . . . . . . . . . . . . . . . . .
ST72361xx-Auto Contents 14.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 14.3 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 15 14.3.1 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 14.3.2 Slave select management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 14.3.3 Master mode operation . . . . . .
Contents ST72361xx-Auto 15.8 15.9 SCI mode register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 15.8.1 Status register (SCISR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 15.8.2 Control register 1 (SCICR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 15.8.3 Control register 2 (SCICR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 15.8.4 Data register (SCIDR) . . . . . . . . . . . .
ST72361xx-Auto 17 18 Contents 16.4.2 Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 16.4.3 Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 16.4.4 Conventional baud rate generation . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 16.4.5 Extended baud rate generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 16.4.
Contents ST72361xx-Auto 18.2 18.1.1 Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 18.1.2 Immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 18.1.3 Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 18.1.4 Indexed (no offset, short, long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 18.1.
ST72361xx-Auto 19.9 Contents 19.8.1 Functional EMS (electromagnetic susceptibility) . . . . . . . . . . . . . . . . . 238 19.8.2 Electromagnetic interference (EMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 19.8.3 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . 239 I/O port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 19.9.1 General characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . .
Contents ST72361xx-Auto 23.2 23.3 Flash/FastROM devices only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273 23.2.1 LINSCI wrong break duration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273 23.2.2 16-bit and 8-bit timer PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275 ROM devices only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275 23.3.1 24 12/279 16-bit timer PWM mode buffering feature change . .
ST72361xx-Auto List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Table 45. Table 46. Table 47.
List of tables Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. Table 56. Table 57. Table 58. Table 59. Table 60. Table 61. Table 62. Table 63. Table 64. Table 65. Table 66. Table 67. Table 68. Table 69. Table 70. Table 71. Table 72. Table 73. Table 74. Table 75. Table 76. Table 77. Table 78. Table 79. Table 80. Table 81. Table 82. Table 83. Table 84. Table 85. Table 86. Table 87. Table 88. Table 89. Table 90. Table 91. Table 92. Table 93. Table 94. Table 95. Table 96. Table 97.
ST72361xx-Auto Table 101. Table 102. Table 103. Table 104. Table 105. Table 106. Table 107. Table 108. Table 109. Table 110. Table 111. Table 112. Table 113. Table 114. Table 115. Table 116. Table 117. Table 118. Table 119. Table 120. List of tables EMS test results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 EMI emissions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
List of figures ST72361xx-Auto List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41. Figure 42. Figure 43.
ST72361xx-Auto Figure 49. Figure 50. Figure 51. Figure 52. Figure 53. Figure 54. Figure 55. Figure 56. Figure 57. Figure 58. Figure 59. Figure 60. Figure 61. Figure 62. Figure 63. Figure 64. Figure 65. Figure 66. Figure 67. Figure 68. Figure 69. Figure 70. Figure 71. Figure 72. Figure 73. Figure 74. Figure 75. Figure 76. Figure 77. Figure 78. Figure 79. Figure 80. Figure 81. Figure 82. Figure 83. Figure 84. Figure 85. Figure 86. Figure 87. Figure 88. Figure 89. Figure 90. Figure 91. Figure 92. Figure 93.
List of figures Figure 101. Figure 102. Figure 103. Figure 104. Figure 105. Figure 106. Figure 107. Figure 108. Figure 109. Figure 110. Figure 111. Figure 112. Figure 113. Figure 114. Figure 115. Figure 116. Figure 117. Figure 118. Figure 119. Figure 120. Figure 121. Figure 122. Figure 123. Figure 124. Figure 125. Figure 126. Figure 127. Figure 128. Figure 129. Figure 130. Figure 131. Figure 132. 18/279 ST72361xx-Auto PLL jitter vs signal frequency(1) . . . . . . . . . . . . . . . . . . . . . . . . . . .
ST72361xx-Auto 1 Description Description The ST72361xx-Auto devices are members of the ST7 microcontroller family designed for automotive mid-range applications with LIN (Local Interconnect Network) interface. All devices are based on a common industry-standard 8-bit core, featuring an enhanced instruction set and are available with Flash or ROM program memory.
Description ST72361xx-Auto Figure 1. Device block diagram option OSC1 OSC2 PWM ART PLL x 2 OSC /2 8-Bit TIMER 16-Bit TIMER VDD VSS CONTROL 8-BIT CORE ALU PORT B ADDRESS AND DATA BUS RESET TLI1 PORT A POWER SUPPLY PROGRAM MEMORY (16 - 60 Kbytes) RAM (1.5 - 2 Kbytes) PORT C PORT D PORT E PORT F SPI LINSCI2 (LIN master) LINSCI1 (LIN master/slave) WINDOW MCC (Clock Control) 1.
ST72361xx-Auto Pin description LQFP 64-pin package pinout PF7 PF6 PD7 / AIN11 PD6 / AIN10 RESET PD5 / LINSCI2_TDO VDD_0 VDDA VSS_0 VSSA PD4 / LINSCI2_RDI PD3 (HS)/ LINSCI2_SCK PF5 TLI PF4 PF3 / AIN9 Figure 2.
Description ST72361xx-Auto LQFP 44-pin package pinout PD7 / AIN11 PD6 / AIN10 RESET PD5 / LINSCI2_TDO 1 VDD_0 VDDA VSS_0 VSSA PD4 / LINSCI2_RDI PD3 (HS) / LINSCI2_SCK PF5 Figure 3.
ST72361xx-Auto LQFP 32-pin package pinout RESET PD5 / LINSCI2_TDO VDD_0 VDDA VSS_0 VSSA PD4 / LINSCI2_RDI PD3 (HS) / LINSCI2_SCK1 Figure 4.
Description ST72361xx-Auto List of abbreviations used in Table 3 Type: I = input, O = output, S = supply In/Output level: CT= CMOS 0.3VDD/0.7VDD with Schmitt trigger TT= TTL 0.
ST72361xx-Auto Table 3.
Description Port Main function Output (after reset) Alternate function X X Port F0 I/O TT X X 45 30 - PF1 / AIN7 I/O TT X X X X X Port F1 ADC analog input 7 46 31 - PF2 / AIN8 I/O TT X X X X X Port F2 ADC analog input 8 47 32 23 PD1 / SCI1_RDI I/O CT X X X Port D1 LINSCI1 receive data input 48 33 24 PD2 / SCI1_TDO I/O CT X X X X Port D2 LINSCI1 transmit data output 49 - - PF3 / AIN9 I/O TT X X X X Port F3 ADC analog input 9 50 - - PF4 I/O TT X
ST72361xx-Auto 2 Register and memory map Register and memory map As shown in Figure 5, the MCU is capable of addressing 64 Kbytes of memories and I/O registers. The available memory locations consist of 128 bytes of register locations, up to 2 Kbytes of RAM and up to 60 Kbytes of user program memory. The RAM space includes up to 256 bytes for the stack from 0100h to 01FFh.The highest address bytes contain the user reset and interrupt vectors.
Register and memory map Table 4.
ST72361xx-Auto Table 4.
Flash program memory ST72361xx-Auto 3 Flash program memory 3.1 Introduction The ST7 dual voltage High Density Flash (HDFlash) is a non-volatile memory that can be electrically erased as a single block or by individual sectors and programmed on a Byte-byByte basis using an external VPP supply. The HDFlash devices can be programmed and erased off-board (plugged in a programming tool) or on-board using ICP (In-Circuit Programming) or IAP (In-Application Programming).
ST72361xx-Auto 3.3.1 Flash program memory Read-out protection Read-out protection, when selected, provides a protection against Program Memory content extraction and against write access to Flash memory. Even if no protection can be considered as totally unbreakable, the feature provides a very high level of protection for a general purpose microcontroller. In Flash devices, this protection is removed by reprogramming the option.
Flash program memory Figure 7. ST72361xx-Auto Typical ICC interface PROGRAMMING TOOL ICC CONNECTOR ICC Cable APPLICATION BOARD (See Note 3) ICC CONNECTOR HE10 CONNECTOR TYPE OPTIONAL (See Note 4) 9 7 5 3 1 10 8 6 4 2 APPLICATION RESET SOURCE See Note 2 10k Note: 3.
ST72361xx-Auto Flash program memory interface on the application board (see Figure 7). For more details on the pin locations, refer to the device pinout description. 3.6 IAP (in-application programming) This mode uses a Bootloader program previously stored in Sector 0 by the user (in ICP mode or by plugging the device in a programming tool). This mode is fully controlled by user software.
Central processing unit ST72361xx-Auto 4 Central processing unit 4.1 Introduction This CPU has a full 8-bit architecture and contains six internal registers allowing efficient 8-bit data manipulation. 4.2 4.
ST72361xx-Auto Central processing unit Figure 8. CPU registers 7 0 ACCUMULATOR RESET VALUE = XXh 7 0 X INDEX REGISTER RESET VALUE = XXh 7 0 Y INDEX REGISTER RESET VALUE = XXh PCH 15 PCL 8 7 0 PROGRAM COUNTER RESET VALUE = RESET VECTOR @ FFFEh-FFFFh 7 0 1 1 I1 H I0 N Z C CONDITION CODE REGISTER RESET VALUE = 1 1 1 X 1 X X X 15 8 7 0 STACK POINTER RESET VALUE = STACK HIGHER ADDRESS X = Undefined Value 4.3.
Central processing unit ST72361xx-Auto This bit is accessed by the JRMI and JRPL instructions. Bit 1 = Z Zero. This bit is set and cleared by hardware. This bit indicates that the result of the last arithmetic, logical or data manipulation is zero. 0: The result of the last operation is different from zero. 1: The result of the last operation is zero. This bit is accessed by the JREQ and JRNE test instructions. Bit 0 = C Carry/borrow. This bit is set and cleared by hardware and software.
ST72361xx-Auto 4.3.5 Central processing unit Stack pointer (SP) Read/ write Reset value: 01 FFh 15 0 8 0 0 0 0 0 0 7 SP7 1 0 SP6 SP5 SP4 SP3 SP2 SP1 SP0 The Stack Pointer is a 16-bit register which is always pointing to the next free location in the stack. It is then decremented after data has been pushed onto the stack and incremented before data is popped from the stack (see Figure 9). Since the stack is 256 bytes deep, the 8 most significant bits are forced by hardware.
Central processing unit Figure 9.
ST72361xx-Auto Supply, reset and clock management 5 Supply, reset and clock management 5.1 Introduction The device includes a range of utility features for securing the application in critical situations (for example, in case of a power brown-out), and reducing the number of external components. An overview is shown in Figure 11. For more details, refer to dedicated parametric section. 5.
Supply, reset and clock management ST72361xx-Auto Figure 11. Clock, reset and supply block diagram / 8000 OSC2 MULTI- fOSC PLL (option) OSCILLATOR OSC1 (MO) 8-BIT TIMER MAIN CLOCK CONTROLLER WITH REALTIME CLOCK (MCC/RTC) fOSC2 fCPU SYSTEM INTEGRITY MANAGEMENT RESET SEQUENCE RESET MANAGER (RSM) WATCHDOG AVD Interrupt Request SICSR AVD AVD LVD 0 IE F RF TIMER (WDG) 0 0 0 WDG RF LOW VOLTAGE VSS DETECTOR VDD (LVD) AUXILIARY VOLTAGE DETECTOR (AVD) 5.
ST72361xx-Auto Supply, reset and clock management output distortion and start-up stabilization time. The loading capacitance values must be adjusted according to the selected oscillator. These oscillators are not stopped during the RESET phase to avoid losing time in the oscillator start-up phase. Table 8. ST7 clock sources External clock Hardware configuration ST7 OSC1 OSC2 Crystal/Ceramic resonators EXTERNAL SOURCE ST7 OSC1 CL1 OSC2 LOAD CAPACITORS 5.5 Reset sequence manager (RSM) 5.5.
Supply, reset and clock management ST72361xx-Auto The reset vector fetch phase duration is two clock cycles. Figure 12. RESET sequence phases RESET Active Phase 5.5.2 INTERNAL RESET 256 or 4096 CLOCK CYCLES FETCH VECTOR Asynchronous external RESET pin The RESET pin is both an input and an open-drain output with integrated RON weak pull-up resistor. This pull-up has no fixed value but varies in accordance with the input voltage. It can be pulled low by external circuitry to reset the device.
ST72361xx-Auto Supply, reset and clock management The device RESET pin acts as an output that is pulled low when VDD < VIT+ (rising edge) or VDD < VIT- (falling edge) as shown in Figure 14. The LVD filters spikes on VDD larger than tg(VDD) to avoid parasitic resets. 5.5.5 Internal watchdog reset The RESET sequence generated by a internal Watchdog counter overflow is shown in Figure 14.
Supply, reset and clock management ST72361xx-Auto The LVD function is illustrated in Figure 15. Provided the minimum VDD value (guaranteed for the oscillator frequency) is above VIT-(LVD), the MCU can only be in two modes: ● under full software control ● in static safe reset In these conditions, secure operation is always ensured for the application without the need for external reset hardware.
ST72361xx-Auto Supply, reset and clock management If trv is greater than 256 or 4096 cycles then: ● If the AVD interrupt is enabled before the VIT+(AVD) threshold is reached, then two AVD interrupts will be received: The first when the AVDIE bit is set and the second when the threshold is reached. ● If the AVD interrupt is enabled after the VIT+(AVD) threshold is reached, then only one AVD interrupt occurs. Figure 16.
Supply, reset and clock management 5.6.5 ST72361xx-Auto Register description System integrity (SI) control/status register (SICSR) Read/Write Reset value: 000x 000x (00h) 7 0 0 AVDIE AVDF LVDRF 0 0 0 WDGRF Bit 7 = Reserved, must be kept cleared. Bit 6 = AVDIE Voltage Detector interrupt enable This bit is set and cleared by software. It enables an interrupt to be generated when the AVDF flag changes (toggles).
ST72361xx-Auto Table 11. Supply, reset and clock management Reset source flags RESET sources LVDRF External RESET pin WDGRF 0 0 Watchdog 1 LVD 1 X Application notes The LVDRF flag is not cleared when another RESET type occurs (external or watchdog), the LVDRF flag remains set to keep trace of the original failure. In this case, a watchdog reset can be detected by software while an external reset can not.
Interrupts ST72361xx-Auto 6 Interrupts 6.
ST72361xx-Auto Interrupts Table 12. Interrupt software priority levels Interrupt software priority Level Level 0 (main) I1 I0 1 0 Low Level 1 1 0 Level 2 0 High Level 3 (= interrupt disable) 1 1 Figure 17.
Interrupts ST72361xx-Auto When an interrupt request is not serviced immediately, it is latched and then processed when its software priority combined with the hardware priority becomes the highest one. Note: 1 The hardware priority is exclusive while the software one is not. This allows the previous process to succeed with only one interrupt. 2 RESET, TRAP and TLI can be considered as having the highest software priority in the decision process.
ST72361xx-Auto Interrupts if the corresponding enable bit is set in the peripheral control register. The general sequence for clearing an interrupt is based on an access to the status register followed by a read or write to an associated register. Note: The clearing sequence resets the internal latch. A pending interrupt (that is, waiting for being serviced) will therefore be lost if the clear sequence is executed. 6.
Interrupts ST72361xx-Auto IT0 TLI IT3 IT4 IT1 SOFTWARE PRIORITY LEVEL TLI IT0 IT1 IT1 IT2 IT2 IT3 RIM IT4 IT4 MAIN MAIN 11 / 10 I1 I0 3 1 1 3 1 1 2 0 0 1 0 1 3 1 1 3 1 1 USED STACK = 20 BYTES HARDWARE PRIORITY IT2 Figure 20. Nested interrupt management 3/0 10 6.5 Interrupt register description 6.5.
ST72361xx-Auto 6.5.2 Interrupts Interrupt software priority registers (ISPRX) Read/ write (bit 7:4 of ISPR3 are read only) Reset value: 1111 1111 (FFh) 7 0 ISPR0 I1_3 I0_3 I1_2 I0_2 I1_1 I0_1 I1_0 I0_0 ISPR1 I1_7 I0_7 I1_6 I0_6 I1_5 I0_5 I1_4 I0_4 ISPR2 I1_11 I0_11 I1_10 I0_10 I1_9 I0_9 I1_8 I0_8 ISPR3 1 1 1 1 I1_13 I0_13 I1_12 I0_12 These four registers contain the interrupt software priority of each interrupt vector.
Interrupts ST72361xx-Auto Table 15.
ST72361xx-Auto Table 16.
Interrupts ST72361xx-Auto 6.6 External interrupts 6.6.1 I/O port interrupt sensitivity The external interrupt sensitivity is controlled by the ISxx bits in the EICR register (Figure 21). This control allows up to four fully independent external interrupt source sensitivities.
ST72361xx-Auto Interrupts Figure 21. External interrupt control bits EICR PORT A [7:0] INTERRUPTS IS00 PAOR.0 PADDR.0 IS01 SENSITIVITY PA0 CONTROL PA0 PA1 PA2 PA3 ei0 INTERRUPT SOURCE PA4 PA5 PA6 PA7 EICR PORT B [5:0] INTERRUPTS IS10 PBOR.0 PBDDR.0 IS11 PB0 PB1 PB2 PB3 PB4 PB5 CONTROL ei1 INTERRUPT SOURCE EICR PORT C [2:1] INTERRUPTS IS20 PCOR.7 PCDDR.7 IS21 SENSITIVITY PC1 CONTROL PORT D [7:6, 4, 1:0] INTERRUPTS PDOR.0 PDDDR.
Interrupts 6.6.2 ST72361xx-Auto Register description External interrupt control register 0 (EICR0) Read/Write Reset value: 0000 0000 (00h) 7 IS31 0 IS30 IS21 IS20 IS11 IS10 IS01 IS00 Bits 7:6 = IS3[1:0] ei3 sensitivity The interrupt sensitivity, defined using the IS3[1:0] bits, is applied to the ei3 external interrupts: Table 17.
ST72361xx-Auto Interrupts Table 19. IS11 Interrupt sensitivity - ei1 IS10 External interrupt sensitivity 0 Falling edge only 1 Rising and falling edge 1 These 2 bits can be written only when I1 and I0 of the CC register are both set to 1 (level 3). Bits 1:0 = IS0[1:0] ei0 sensitivity The interrupt sensitivity, defined using the IS0[1:0] bits, is applied to the ei0 external interrupts: Table 20.
Interrupts Table 21. ST72361xx-Auto Nested interrupts register map and reset values Address (Hex.
ST72361xx-Auto Power saving modes 7 Power saving modes 7.1 Introduction To give a large measure of flexibility to the application in terms of power consumption, five main power saving modes are implemented in the ST7 (see Figure 22): ● Slow ● Wait (and Slow-Wait) ● Active Halt ● Auto Wake-up From Halt (AWUFH) ● Halt After a RESET the normal operating mode is selected by default (RUN mode).
Power saving modes ST72361xx-Auto In this mode, the master clock frequency (fOSC2) can be divided by 2, 4, 8 or 16. The CPU and peripherals are clocked at this lower frequency (fCPU). Note: SLOW-WAIT mode is activated by entering WAIT mode while the device is in SLOW mode. Figure 23. SLOW mode clock transitions fOSC2/2 fOSC2/4 fOSC2 fCPU MCCSR fOSC2 CP1:0 00 01 SMS NEW SLOW FREQUENCY REQUEST 7.
ST72361xx-Auto Power saving modes Figure 24. WAIT mode flow-chart WFI INSTRUCTION OSCILLATOR PERIPHERALS CPU I[1:0] BITS ON ON OFF 10 N RESET Y N INTERRUPT Y OSCILLATOR PERIPHERALS CPU I[1:0] BITS ON OFF ON 10 256 OR 4096 CPU CLOCK CYCLE DELAY OSCILLATOR ON PERIPHERALS ON CPU ON I[1:0] BITS XX 1) FETCH RESET VECTOR OR SERVICE INTERRUPT Note: Before servicing an interrupt, the CC register is pushed on the stack.
Power saving modes ST72361xx-Auto system is enabled, can generate a Watchdog RESET (see Section 22.1: Introduction for more details). Figure 25. HALT timing overview RUN HALT HALT INSTRUCTION [MCCSR.OIE=0] 256 OR 4096 CPU CYCLE DELAY RUN RESET OR INTERRUPT FETCH VECTOR Figure 26. HALT mode flow-chart HALT INSTRUCTION (MCCSR.OIE=0) (AWUCSR.
ST72361xx-Auto Power saving modes Halt mode recommendations 7.5 ● Make sure that an external event is available to wake up the microcontroller from Halt mode. ● When using an external interrupt to wake up the microcontroller, reinitialize the corresponding I/O as “Input Pull-up with Interrupt” before executing the HALT instruction. The main reason for this is that the I/O may be wrongly configured due to external interference or by an unforeseen logical condition.
Power saving modes Note: ST72361xx-Auto As soon as active halt is enabled, executing a HALT instruction while the Watchdog is active does not generate a RESET. This means that the device cannot spend more than a defined delay in this power saving mode. Figure 27. ACTIVE HALT timing overview RUN ACTIVE 256 OR 4096 CYCLE HALT DELAY (AFTER RESET) RUN RESET OR HALT INTERRUPT INSTRUCTION (Active Halt enabled) FETCH VECTOR Figure 28. ACTIVE HALT mode flow-chart HALT INSTRUCTION (MCCSR.OIE=1) (AWUCSR.
ST72361xx-Auto Power saving modes It is entered by executing the HALT instruction when the AWUEN bit in the AWUCSR register has been set and the OIE bit in the MCCSR register is cleared (see Section 10: Main clock controller with real time clock MCC/RTC for more details). Figure 29. AWUFH mode block diagram AWU RC oscillator fAWU_RC /64 divider to Timer input capture AWUFH prescaler /1 ..
Power saving modes ST72361xx-Auto Figure 30. AWUF halt timing diagram tAWU RUN MODE HALT MODE 256 or 4096 tCPU RUN MODE fCPU fAWU_RC Clear by software AWUFH interrupt Figure 31. AWUFH mode flow-chart HALT INSTRUCTION (MCCSR.OIE=0) (AWUCSR.
ST72361xx-Auto 7.6.1 Power saving modes Register description AWUFH control/status register (AWUCSR) Read/Write (except bit 2 read only) Reset value: 0000 0000 (00h) 7 0 0 0 0 0 0 AWUF AWUM AWUEN Bits 7:3 = Reserved. Bit 2 = AWUF Auto Wake-Up Flag This bit is set by hardware when the AWU module generates an interrupt and cleared by software on reading AWUCSR.
Power saving modes Table 23. ST72361xx-Auto AWUPR prescaler (continued) AWUPR[7:0] Dividing factor FEh 254 FFh 255 In AWU mode, the period that the MCU stays in Halt Mode (tAWU in Figure 30) is defined by 1 t AWU = 64 AWUP ---------------------- + t RCSTRT t AWURC This prescaler register can be programmed to modify the time that the MCU stays in Halt mode before waking up automatically.
ST72361xx-Auto I/O ports 8 I/O ports 8.1 Introduction The I/O ports offer different functional modes: ● transfer of data through digital inputs and outputs and for specific pins: ● external interrupt generation ● alternate signal input/output for the on-chip peripherals. An I/O port contains up to 8 pins. Each pin can be programmed independently as digital input (with or without interrupt generation) or digital output. 8.
I/O ports ST72361xx-Auto Each external interrupt vector is linked to a dedicated group of I/O port pins (see pinout description and interrupt section). If several input pins are selected simultaneously as interrupt sources, these are first detected according to the sensitivity bits in the EICR register and then logically ORed.
ST72361xx-Auto I/O ports Figure 32. I/O port general block diagram ALTERNATE OUTPUT REGISTER ACCESS 1 VDD 0 ALTERNATE ENABLE P-BUFFER (see table below) PULL-UP (see table below) DR VDD DDR PULL-UP CONDITION DATA BUS OR PAD If implemented OR SEL N-BUFFER DIODES (see table below) DDR SEL DR SEL ANALOG INPUT CMOS SCHMITT TRIGGER 1 0 ALTERNATE INPUT EXTERNAL INTERRUPT SOURCE (eix) Table 26.
I/O ports ST72361xx-Auto Table 27.
ST72361xx-Auto I/O ports Warning: 8.3 The analog input voltage level must be within the limits stated in the absolute maximum ratings. I/O port implementation The hardware implementation on each I/O port depends on the settings in the DDR and OR registers and specific feature of the I/O port such as ADC Input or true open drain. Switching these I/O ports from one state to another should be done in a sequence that prevents unwanted side effects. Recommended safe transitions are illustrated in Figure 33.
I/O ports 8.4.2 ST72361xx-Auto Interrupt ports Table 29. Configuration of PA0, 2, 4, 6; PB0, 2,4; PC1; PD0,6 (with pull-up) Mode DDR Floating input OR 0 0 Pull-up interrupt input 1 Open drain output 0 1 Push-pull output Table 30.
ST72361xx-Auto 8.4.3 I/O ports Pull-up input port Table 31. Configuration of PC4 Mode pull-up input The PC4 port cannot operate as a general purpose output. If DDR = 1 it is still possible to read the port through the DR register. Table 32.
I/O ports ST72361xx-Auto Table 32. Port configuration (continued) Input Port Output Pin name OR = 0 OR = 1 PD0 pull-up interrupt (ei3) PD1 floating interrupt (ei3) PD3:2 Port D 8.5 OR = 1 open drain push-pull pull-up floating PD4 floating interrupt (ei3) PD5 pull-up PD6 pull-up interrupt (ei3) PD7 floating interrupt (ei3) Port E PE7:0 floating (TTL) pull-up (TTL) open drain push-pull Port F PF7:0 floating (TTL) pull-up (TTL) open drain push-pull Low power modes Table 33.
ST72361xx-Auto Table 35. Address (Hex.
Window watchdog (WWDG) ST72361xx-Auto 9 Window watchdog (WWDG) 9.1 Introduction The Window Watchdog is used to detect the occurrence of a software fault, usually generated by external interference or by unforeseen logical conditions, which causes the application program to abandon its normal sequence. The Watchdog circuit generates an MCU reset on expiry of a programmed time period, unless the program refreshes the contents of the downcounter before the T6 bit becomes cleared.
ST72361xx-Auto Window watchdog (WWDG) Figure 34.
Window watchdog (WWDG) 9.4 ST72361xx-Auto Using halt mode with the WDG If Halt mode with Watchdog is enabled by option byte (no watchdog reset on HALT instruction), it is recommended before executing the HALT instruction to refresh the WDG counter, to avoid an unexpected WDG reset immediately after waking up the microcontroller. 9.
ST72361xx-Auto Window watchdog (WWDG) Figure 36. Exact timeout duration (tmin and tmax) WHERE: tmin0 = (LSB + 128) x 64 x tOSC2 tmax0 = 16384 x tOSC2 tOSC2 = 125ns if fOSC2 = 8 MHz CNT = Value of T[5:0] bits in the WDGCR register (6 bits) MSB and LSB are values from the table below depending on the timebase selected by the TB[1:0] bits in the MCCSR register TB1 Bit (MCCSR Reg.) TB0 Bit (MCCSR Reg.
Window watchdog (WWDG) ST72361xx-Auto Figure 37. Window watchdog timing diagram T[5:0] CNT downcounter WDGWR 3Fh Refresh not allowed Refresh Window time (step = 16384/fOSC2) T6 bit Reset 9.6 Low power modes Table 36. Effect of low power modes on WDG Mode Description SLOW No effect on Watchdog: the downcounter continues to decrement at normal speed. WAIT No effect on Watchdog: the downcounter continues to decrement.
ST72361xx-Auto 9.8 Window watchdog (WWDG) Using halt mode with the WDG (WDGHALT option) The following recommendation applies if Halt mode is used when the watchdog is enabled. ● 9.9 Before executing the HALT instruction, refresh the WDG counter, to avoid an unexpected WDG reset immediately after waking up the microcontroller. Interrupts None. 9.10 Register description 9.10.
Window watchdog (WWDG) Table 37. 86/279 ST72361xx-Auto Watchdog timer register map and reset values Address (Hex.
ST72361xx-Auto 10 Main clock controller with real time clock MCC/RTC Main clock controller with real time clock MCC/RTC The Main Clock Controller consists of three different functions: ● a programmable CPU clock prescaler ● a clock-out signal to supply external devices ● a real time clock timer with interrupt capability Each function can be used independently and simultaneously. 10.
Main clock controller with real time clock MCC/RTC 10.4 Low power modes Table 38. Effect of low power modes on MCC/RTC Mode ST72361xx-Auto Description WAIT No effect on MCC/RTC peripheral. MCC/RTC interrupt cause the device to exit from WAIT mode. ACTIVE HALT No effect on MCC/RTC counter (OIE bit is set), the registers are frozen. MCC/RTC interrupt cause the device to exit from ACTIVE HALT mode. HALT and AWUF HALT MCC/RTC counter and registers are frozen.
ST72361xx-Auto Main clock controller with real time clock MCC/RTC Table 40. CPU clock frequency in SLOW mode fCPU in SLOW mode CP1 fOSC2 / 2 CP0 0 0 fOSC2 / 4 1 fOSC2/ 8 0 1 fOSC2 / 16 1 Bit 4 = SMS Slow mode select This bit is set and cleared by software. 0: Normal mode. fCPU = fOSC2 1: Slow mode. fCPU is given by CP1, CP0 See Section 7.2: Slow mode and Section 10: Main clock controller with real time clock MCC/RTC for more details.
Main clock controller with real time clock MCC/RTC Caution: The BRES and BSET instructions must not be used on the MCCSR register to avoid unintentionally clearing the OIF bit. Table 42. Address (Hex.
ST72361xx-Auto PWM auto-reload timer (ART) 11 PWM auto-reload timer (ART) 11.1 Introduction The Pulse Width Modulated Auto-Reload Timer on-chip peripheral consists of an 8-bit autoreload counter with compare/capture capabilities and of a 7-bit prescaler clock source.
PWM auto-reload timer (ART) ST72361xx-Auto 11.2 Functional description 11.2.1 Counter The free running 8-bit counter is fed by the output of the prescaler, and is incremented on every rising edge of the clock signal. It is possible to read or write the contents of the counter on the fly by reading or writing the Counter Access register (ARTCAR). When a counter overflow occurs, the counter is automatically reloaded with the contents of the ARTARR register (the prescaler is not affected). 11.2.
ST72361xx-Auto PWM auto-reload timer (ART) Figure 40. Output compare control fCOUNTER ARTARR=FDh COUNTER FDh FEh FFh OCRx FDh FEh FFh FDh FDh FFh FEh FDh PWMDCRx FEh FEh PWMx 11.2.5 Independent PWM signal generation This mode allows up to four Pulse Width Modulated signals to be generated on the PWMx output pins with minimum core processing overhead. This function is stopped during HALT mode.
PWM auto-reload timer (ART) ST72361xx-Auto Figure 42. PWM signal from 0% to 100% duty cycle fCOUNTER ARTARR = FDh COUNTER FDh FEh FFh FDh FEh FFh FDh FEh PWMx OUTPUT WITH OEx=1 AND OPx=0 OCRx=FCh OCRx=FDh OCRx=FEh OCRx=FFh t 11.2.6 Output compare and Time base interrupt On overflow, the OVF flag of the ARTCSR register is set and an overflow interrupt request is generated if the overflow interrupt enable bit, OIE, in the ARTCSR register, is set. The OVF flag must be reset by the user software.
ST72361xx-Auto PWM auto-reload timer (ART) Each input capture can generate an interrupt independently on a selected input signal transition. This event is flagged by a set of the corresponding CFx bits of the Input Capture Control/Status register (ARTICCSR). These input capture interrupts are enabled through the CIEx bits of the ARTICCSR register. The active transition (falling or rising edge) is software programmable through the CSx bits of the ARTICCSR register.
PWM auto-reload timer (ART) ST72361xx-Auto Figure 45. Input capture timing diagram, fCOUNTER = fCPU / 4 fCPU fCOUNTER COUNTER 05h 04h 03h ARTICx PIN INTERRUPT ICAP SAMPLED CFx FLAG 04h xxh ICRx REGISTER t fCPU fCOUNTER COUNTER 05h 04h 03h INTERRUPT ARTICx PIN ICAP SAMPLED CFx FLAG 05h xxh ICRx REGISTER t 11.2.9 External interrupt capability This mode allows the Input capture capabilities to be used as external interrupt sources.
ST72361xx-Auto 11.3 PWM auto-reload timer (ART) Register description Control/status register (ARTCSR) Read/Write Reset value: 0000 0000 (00h) 7 0 EXCL CC2 CC1 CC0 TCE FCRL OIE OVF Bit 7 = EXCL External Clock This bit is set and cleared by software. It selects the input clock for the 7-bit prescaler. 0: CPU clock. 1: External clock. Bit 6:4 = CC[2:0] Counter Clock Control These bits are set and cleared by software. They determine the prescaler division ratio from fINPUT. Table 43.
PWM auto-reload timer (ART) ST72361xx-Auto Bit 0 = OVF Overflow Flag This bit is set by hardware and cleared by software reading the ARTCSR register. It indicates the transition of the counter from FFh to the ARTARR value . 0: New transition not yet reached 1: Transition reached Counter Access Register (ARTCAR) Read/Write Reset value: 0000 0000 (00h) 7 0 CA7 CA6 CA5 CA4 CA3 CA2 CA1 CA0 Bit 7:0 = CA[7:0] Counter Access Data These bits can be set and cleared either by hardware or by software.
ST72361xx-Auto PWM auto-reload timer (ART) PWM control register (PWMCR) Read/write Reset value: 0000 0000 (00h) 7 0 OE3 OE2 OE1 OE0 OP3 OP2 OP1 OP0 Bit 7:4 = OE[3:0] PWM Output Enable These bits are set and cleared by software. They enable or disable the PWM output channels independently acting on the corresponding I/O pin. 0: PWM output disabled. 1: PWM output enabled. Bit 3:0 = OP[3:0] PWM Output Polarity These bits are set and cleared by software.
PWM auto-reload timer (ART) ST72361xx-Auto 7 0 0 0 CS2 CS1 CIE2 CIE1 CF2 CF1 Bit 7:6 = Reserved, always read as 0. Bit 5:4 = CS[2:1] Capture Sensitivity These bits are set and cleared by software. They determine the trigger event polarity on the corresponding input capture channel. 0: Falling edge triggers capture on channel x. 1: Rising edge triggers capture on channel x. Bit 3:2 = CIE[2:1] Capture Interrupt Enable These bits are set and cleared by software.
ST72361xx-Auto Table 46. Address (Hex.
16-bit timer ST72361xx-Auto 12 16-bit timer 12.1 Introduction The timer consists of a 16-bit free-running counter driven by a programmable prescaler. It may be used for a variety of purposes, including pulse length measurement of up to two input signals (input capture) or generation of up to two output waveforms (output compare and PWM). Pulse lengths and waveform periods can be modulated from a few microseconds to several milliseconds using the timer prescaler and the CPU clock prescaler.
ST72361xx-Auto 16-bit timer 12.3 Functional description 12.3.1 Counter The main block of the Programmable Timer is a 16-bit free running upcounter and its associated 16-bit registers. The 16-bit registers are made up of two 8-bit registers called high and low. Counter Register (CR): ● Counter High Register (CHR) is the most significant byte (MS Byte). ● Counter Low Register (CLR) is the least significant byte (LS Byte).
16-bit timer ST72361xx-Auto Figure 47.
ST72361xx-Auto 16-bit timer The user must read the MS Byte first, then the LS Byte value is buffered automatically. This buffered value remains unchanged until the 16-bit read sequence is completed, even if the user reads the MS Byte several times. After a complete reading sequence, if only the CLR register or ACLR register are read, they return the LS Byte of the count value at the time of the read.
16-bit timer ST72361xx-Auto Figure 49. Counter timing diagram, internal clock divided by 2 CPU CLOCK INTERNAL RESET TIMER CLOCK FFFD FFFE FFFF 0000 COUNTER REGISTER 0001 0002 0003 TIMER OVERFLOW FLAG (TOF) Figure 50. Counter timing diagram, internal clock divided by 4 CPU CLOCK INTERNAL RESET TIMER CLOCK COUNTER REGISTER FFFC FFFD 0000 0001 TIMER OVERFLOW FLAG (TOF) Figure 51.
ST72361xx-Auto 16-bit timer The active transition is software programmable through the IEDGi bit in the control register (CRi). Timing resolution is one count of the free running counter: (fCPU/CC[1:0]). 12.3.4 Procedure To use the input capture function select the following in the CR2 register: ● Select the timer clock (CC[1:0]) (see Table 50).
16-bit timer ST72361xx-Auto Figure 52. Input capture block diagram ICAP1 pin ICAP2 pin (Control Register 1) CR1 EDGE DETECT CIRCUIT2 EDGE DETECT CIRCUIT1 ICIE IEDG1 (Status Register) SR IC2R Register IC1R Register ICF1 ICF2 0 0 0 (Control Register 2) CR2 16-BIT 16-BIT FREE RUNNING COUNTER CC1 CC0 IEDG2 Figure 53. Input capture timing diagram TIMER CLOCK COUNTER REGISTER FF01 FF02 FF03 ICAPi PIN ICAPi FLAG FF03 ICAPi REGISTER Note: The rising edge is the active edge. 12.3.
ST72361xx-Auto 16-bit timer These registers are readable and writable and are not affected by the timer hardware. A reset event changes the OCiR value to 8000h. Timing resolution is one count of the free running counter: (fCPU/CC[1:0]). 12.3.6 Procedure To use the output compare function, select the following in the CR2 register: ● Set the OCiE bit if an output is needed then the OCMPi pin is dedicated to the output compare i signal. ● Select the timer clock (CC[1:0]) (see Table 50).
16-bit timer ST72361xx-Auto The following procedure is recommended to prevent the OCFi bit from being set between the time it is read and the write to the OCiR register: Note: 12.3.7 ● Write to the OCiHR register (further compares are inhibited). ● Read the SR register (first step of the clearance of the OCFi bit, which may be already set). ● Write to the OCiLR register (enables the output compare function and clears the OCFi bit).
ST72361xx-Auto 16-bit timer Figure 55. Output compare timing diagram, fTIMER = fCPU/2 INTERNAL CPU CLOCK TIMER CLOCK COUNTER REGISTER 2ECF 2ED0 OUTPUT COMPARE REGISTER i (OCRi) 2ED1 2ED2 2ED3 2ED4 2ED3 OUTPUT COMPARE FLAG i (OCFi) OCMPi PIN (OLVLi = 1) Figure 56.
16-bit timer ST72361xx-Auto 3. Select the following in the CR2 register: – Set the OC1E bit, the OCMP1 pin is then dedicated to the Output Compare 1 function. – Set the OPM bit. – Select the timer clock CC[1:0] (see Table 50).
ST72361xx-Auto Note: 16-bit timer 1 The OCF1 bit cannot be set by hardware in One Pulse mode but the OCF2 bit can generate an Output Compare interrupt. 2 When the Pulse Width Modulation (PWM) and One Pulse mode (OPM) bits are both set, the PWM mode is the only active one. 3 If OLVL1 = OLVL2 a continuous signal will be seen on the OCMP1 pin. 4 The ICAP1 pin can not be used to perform input capture.
16-bit timer ST72361xx-Auto Procedure To use Pulse Width Modulation mode: 1. Load the OC2R register with the value corresponding to the period of the signal using the formula in the opposite column. 2. Load the OC1R register with the value corresponding to the period of the pulse if (OLVL1 = 0 and OLVL2 = 1) using the formula in the opposite column. 3. Select the following in the CR1 register: 4.
ST72361xx-Auto fEXT 16-bit timer = External timer clock frequency (in hertz) The Output Compare 2 event causes the counter to be initialized to FFFCh (See Figure 58) Note: 12.4 1 After a write instruction to the OCiHR register, the output compare function is inhibited until the OCiLR register is also written. 2 The OCF1 and OCF2 bits cannot be set by hardware in PWM mode therefore the Output Compare interrupt is inhibited.
16-bit timer ST72361xx-Auto Note: The 16-bit Timer interrupt events are connected to the same interrupt vector (see Interrupts chapter). These events generate an interrupt if the corresponding Enable Control Bit is set and the interrupt mask in the CC register is reset (RIM instruction). 12.6 Summary of timer modes Table 49.
ST72361xx-Auto 16-bit timer Bit 5 = TOIE Timer Overflow Interrupt Enable. 0: Interrupt is inhibited. 1: A timer interrupt is enabled whenever the TOF bit of the SR register is set. Bit 4 = FOLV2 Forced Output Compare 2. This bit is set and cleared by software. 0: No effect on the OCMP2 pin. 1:Forces the OLVL2 bit to be copied to the OCMP2 pin, if the OC2E bit is set and even if there is no successful comparison. Bit 3 = FOLV1 Forced Output Compare 1. This bit is set and cleared by software.
16-bit timer ST72361xx-Auto Bit 5 = OPM One Pulse Mode. 0: One Pulse mode is not active. 1: One Pulse mode is active, the ICAP1 pin can be used to trigger one pulse on the OCMP1 pin; the active transition is given by the IEDG1 bit. The length of the generated pulse depends on the contents of the OC1R register. Bit 4 = PWM Pulse Width Modulation. 0: PWM mode is not active.
ST72361xx-Auto 16-bit timer Bit 6 = OCF1 Output Compare Flag 1. 0: nomatch (reset value). 1: the content of the free running counter has matched the content of the OC1R register. To clear this bit, first read the SR register, then read or write the low byte of the OC1R (OC1LR) register. Bit 5 = TOF Timer Overflow Flag. 0: No timer overflow (reset value). 1:The free running counter rolled over from FFFFh to 0000h.
16-bit timer 12.7.5 ST72361xx-Auto Input capture 1 low register (IC1LR) Read only Reset value: Undefined This is an 8-bit read only register that contains the low part of the counter value (transferred by the input capture 1 event). 12.7.6 7 0 MSB LSB Output compare 1 high register (OC1HR) Read/ write Reset value: 1000 0000 (80h) This is an 8-bit register that contains the high part of the value to be compared to the CHR register. 12.7.
ST72361xx-Auto 12.7.9 16-bit timer Output compare 2 low register (OC2LR) Read/ write Reset value: 0000 0000 (00h) This is an 8-bit register that contains the low part of the value to be compared to the CLR register. 12.7.10 7 0 MSB LSB Counter high register (CHR) Read only Reset value: 1111 1111 (FFh) This is an 8-bit register that contains the high part of the counter value. 12.7.
16-bit timer 12.7.13 ST72361xx-Auto Alternate counter low register (ACLR) Read only Reset value: 1111 1100 (FCh) This is an 8-bit register that contains the low part of the counter value. A write to this register resets the counter. An access to this register after an access to CSR register does not clear the TOF bit in the CSR register. 12.7.
ST72361xx-Auto Table 51. Address (Hex.
8-bit timer (TIM8) ST72361xx-Auto 13 8-bit timer (TIM8) 13.1 Introduction The timer consists of a 8-bit free-running counter driven by a programmable prescaler. It may be used for a variety of purposes, including pulse length measurement of up to two input signals (input capture) or generation of up to two output waveforms (output compare and PWM). Pulse lengths and waveform periods can be modulated from a few microseconds to several milliseconds using the timer prescaler and the clock prescaler. 13.
ST72361xx-Auto 8-bit timer (TIM8) Writing in the CTR register or ACTR register resets the free running counter to the FCh value. Both counters have a reset value of FCh (this is the only value which is reloaded in the 8-bit timer). The reset value of both counters is also FCh in One Pulse mode and PWM mode. The timer clock depends on the clock control bits of the CR2 register, as shown in Table 55.
8-bit timer (TIM8) ST72361xx-Auto Figure 59.
ST72361xx-Auto Note: 8-bit timer (TIM8) 1. Reading the SR register while the TOF bit is set. 2. An access (read or write) to the CTR register. The TOF bit is not cleared by accesses to ACTR register. The advantage of accessing the ACTR register rather than the CTR register is that it allows simultaneous use of the overflow function and reading the free running counter at random times (for example, to measure elapsed time) without the risk of clearing the TOF bit erroneously.
8-bit timer (TIM8) 13.3.2 ST72361xx-Auto Input capture In this section, the index, i, may be 1 or 2 because there are two input capture functions in the 8-bit timer. The two 8-bit input capture registers (IC1R and IC2R) are used to latch the value of the free running counter after a transition is detected on the ICAPi pin (see Figure 63). ICiR register is a read-only register. The active transition is software programmable through the IEDGi bit of Control Registers (CRi).
ST72361xx-Auto 8-bit timer (TIM8) Moreover if one of the ICAPi pins is configured as an input and the second one as an output, an interrupt can be generated if the user toggles the output pin and if the ICIE bit is set. 6 The TOF bit can be used with interrupt generation in order to measure events that go beyond the timer range (FFh). Figure 63.
8-bit timer (TIM8) ST72361xx-Auto These registers are readable and writable and are not affected by the timer hardware. A reset event changes the OCiR value to 00h. Timing resolution is one count of the free running counter: (fCPU/CC[1:0]). Procedure To use the output compare function, select the following in the CR2 register: ● Set the OCiE bit if an output is needed then the OCMPi pin is dedicated to the output compare i signal. ● Select the timer clock (CC[1:0]) (see Table 55).
ST72361xx-Auto 8-bit timer (TIM8) When the timer clock is fCPU/4, fCPU/8 or fCPU/8000, OCFi and OCMPi are set while the counter value equals the OCiR register value plus 1 (see Figure 67). 13.3.4 4 The output compare functions can be used both for generating external events on the OCMPi pins even if the input capture mode is also used.
8-bit timer (TIM8) ST72361xx-Auto Figure 67. Output compare timing diagram, fTIMER = fCPU/4 fCPU CLOCK TIMER CLOCK COUNTER REGISTER CF D0 OUTPUT COMPARE REGISTER i (OCRi) D1 D2 D3 D4 D3 COMPARE REGISTER i LATCH OUTPUT COMPARE FLAG i (OCFi) OCMPi PIN (OLVLi = 1) 13.3.5 One pulse mode One Pulse mode enables the generation of a pulse when an external event occurs. This mode is selected via the OPM bit in the CR2 register.
ST72361xx-Auto 8-bit timer (TIM8) One pulse mode cycle When event occurs on ICAP1 ICR1 = Counter OCMP1 = OLVL2 Counter is reset to FCh ICF1 bit is set When Counter = OC1R OCMP1 = OLVL1 Then, on a valid event on the ICAP1 pin, the counter is initialized to FCh and OLVL2 bit is loaded on the OCMP1 pin, the ICF1 bit is set and the value FFFDh is loaded in the IC1R register. Because the ICF1 bit is set when an active edge occurs, an interrupt can be generated if the ICIE bit is set.
8-bit timer (TIM8) ST72361xx-Auto Figure 68. One pulse mode timing example COUNTER D3 F8 IC1R F8 FC FD FE D0 D1 D2 FC FD D3 ICAP1 OLVL2 OCMP1 OLVL1 OLVL2 compare1 Note: IEDG1 = 1, OC1R = D0h, OLVL1 = 0, OLVL2 = 1 Figure 69. Pulse width modulation mode timing example COUNTER E2 FC FD FE D0 D1 OLVL2 OCMP1 compare2 D2 OLVL1 compare1 E2 FC OLVL2 compare2 Note: OC1R = D0h, OC2R = E2, OLVL1 = 0, OLVL2 = 1 13.3.
ST72361xx-Auto 8-bit timer (TIM8) 1. Load the OC2R register with the value corresponding to the period of the signal using the formula in the opposite column. 2. Load the OC1R register with the value corresponding to the period of the pulse if (OLVL1 = 0 and OLVL2 = 1) using the formula in the opposite column. 3. Select the following in the CR1 register: 4. – Using the OLVL1 bit, select the level to be applied to the OCMP1 pin after a successful comparison with the OC1R register.
8-bit timer (TIM8) ST72361xx-Auto set and IC2R can be loaded) but the user must take care that the counter is reset each period and ICF1 can also generates interrupt if ICIE is set. 4 13.4 When the Pulse Width Modulation (PWM) and One Pulse Mode (OPM) bits are both set, the PWM mode is the only active one. Low power modes Table 52. Effect of low power modes on TIM8 Mode 13.5 Description WAIT No effect on 8-bit Timer. Timer interrupts cause the device to exit from WAIT mode.
ST72361xx-Auto 13.6 8-bit timer (TIM8) Summary of timer modes Table 54. Timer modes Available resources Modes Input capture 1 Input capture 2 Output compare 1 Output compare 2 Yes Yes Yes Yes Input Capture (1 and/or 2) Output Compare (1 and/or 2) Not Recommended(1) One Pulse Mode Partially(2) No No Not Recommended(3) PWM Mode No 1. See note 4 in One pulse mode. 2. See note 5 in One pulse mode. 3. See note 4 in Pulse width modulation mode. 13.
8-bit timer (TIM8) ST72361xx-Auto Bit 4 = FOLV2 Forced Output Compare 2. This bit is set and cleared by software. 0: No effect on the OCMP2 pin. 1:Forces the OLVL2 bit to be copied to the OCMP2 pin, if the OC2E bit is set and even if there is no successful comparison. Bit 3 = FOLV1 Forced Output Compare 1. This bit is set and cleared by software. 0: No effect on the OCMP1 pin. 1: Forces OLVL1 to be copied to the OCMP1 pin, if the OC1E bit is set and even if there is no successful comparison.
ST72361xx-Auto 8-bit timer (TIM8) Bit 4 = PWM Pulse Width Modulation. 0: PWM mode is not active. 1: PWM mode is active, the OCMP1 pin outputs a programmable cyclic signal; the length of the pulse depends on the value of OC1R register; the period depends on the value of OC2R register. Bit 3, 2 = CC[1:0] Clock Control. The timer clock mode depends on these bits: Table 55. Clock control bits Timer clock CC1 CC0 fCPU / 4 0 0 fCPU / 2 0 1 fCPU / 8 1 0 1 1 fOSC2 / 1.
8-bit timer (TIM8) Note: ST72361xx-Auto Reading or writing the ACTR register does not clear TOF. Bit 4 = ICF2 Input Capture Flag 2. 0: no input capture (reset value). 1: an input capture has occurred on the ICAP2 pin. To clear this bit, first read the SR register, then read or write the IC2R register. Bit 3 = OCF2 Output Compare Flag 2. 0: no match (reset value). 1: the content of the free running counter has matched the content of the OC2R register.
ST72361xx-Auto 13.7.6 8-bit timer (TIM8) Output compare 2 register (OC2R) Read/ write Reset value: 0000 0000 (00h) This is an 8-bit register that contains the value to be compared to the CTR register. 13.7.7 7 0 MSB LSB Counter register (CTR) Read only Reset value: 1111 1100 (FCh) This is an 8-bit register that contains the counter value. A write to this register resets the counter. An access to this register after accessing the CSR register clears the TOF bit. 13.7.
8-bit timer (TIM8) 13.8 ST72361xx-Auto 8-bit timer register map Address (Hex.
ST72361xx-Auto Serial peripheral interface (SPI) 14 Serial peripheral interface (SPI) 14.1 Introduction The Serial Peripheral Interface (SPI) allows full-duplex, synchronous, serial communication with external devices. An SPI system may consist of a master and one or more slaves or a system in which devices may be either masters or slaves. 14.
Serial peripheral interface (SPI) ST72361xx-Auto Figure 70. Serial peripheral interface block diagram Data/Address Bus Read SPIDR Interrupt request Read Buffer MOSI MISO 8-Bit Shift Register SPICSR 7 SPIF WCOL OVR MODF 0 SOD SSM 0 SSI Write SOD bit SS SPI STATE CONTROL SCK 7 SPIE 1 0 SPICR 0 SPE SPR2 MSTR CPOL CPHA SPR1 SPR0 MASTER CONTROL SERIAL CLOCK GENERATOR SS 14.3.
ST72361xx-Auto Serial peripheral interface (SPI) Figure 71. Single master/ single slave application SLAVE MASTER MSBit LSBit 8-BIT SHIFT REGISTER SPI CLOCK GENERATOR MSBit MISO MISO MOSI MOSI SCK SS LSBit 8-BIT SHIFT REGISTER SCK +5V SS Not used if SS is managed by software 14.3.2 Slave select management As an alternative to using the SS pin to control the Slave Select signal, the application can choose to manage the Slave Select signal by software.
Serial peripheral interface (SPI) ST72361xx-Auto Figure 73. Hardware/software slave select management SSM bit 14.3.3 SSI bit 1 SS external pin 0 SS internal Master mode operation In master mode, the serial clock is output on the SCK pin. The clock frequency, polarity and phase are configured by software (refer to the description of the SPICSR register).
ST72361xx-Auto 14.3.5 Serial peripheral interface (SPI) Slave mode operation In slave mode, the serial clock is received on the SCK pin from the master device. To operate the SPI in slave mode: 1. Write to the SPICSR register to perform the following actions: – Select the clock polarity and clock phase by configuring the CPOL and CPHA bits (see Figure 74). Note: The slave must have the same CPOL and CPHA settings as the master. – 2. 14.3.
Serial peripheral interface (SPI) ST72361xx-Auto MISO pin and the MOSI pin are directly connected between the master and the slave device. Note: If CPOL is changed at the communication byte boundaries, the SPI must be disabled by resetting the SPE bit. Figure 74.
ST72361xx-Auto Serial peripheral interface (SPI) Clearing the MODF bit is done through a software sequence: Note: 1. A read access to the SPICSR register while the MODF bit is set. 2. A write to the SPICR register. To avoid any conflicts in an application with multiple slaves, the SS pin must be pulled high during the MODF bit clearing sequence. The SPE and MSTR bits may be restored to their original state during or after this clearing sequence.
Serial peripheral interface (SPI) ST72361xx-Auto Figure 75.
ST72361xx-Auto Serial peripheral interface (SPI) Figure 76. Single master / multiple slave configuration SS SCK Slave Device SS SCK Slave Device SS SCK Slave Device SS SCK Slave Device MOSI MISO MOSI MISO MOSI MISO MOSI MISO SCK Master Device 5V 14.6 Ports MOSI MISO SS Low power modes Table 56. Effect of low power modes on SPI Mode Description WAIT No effect on SPI. SPI interrupt events cause the device to exit from WAIT mode. HALT SPI registers are frozen.
Serial peripheral interface (SPI) 14.7 ST72361xx-Auto Interrupts Table 57. SPI interrupt control and wake-up capability Event flag Interrupt event SPI End of Transfer Event SPIF Master Mode Fault Event MODF Enable control bit Exit from wait Exit from halt Yes SPIE Yes No Overrun Error OVR Note: The SPI interrupt events are connected to the same interrupt vector (see Interrupts chapter).
ST72361xx-Auto Serial peripheral interface (SPI) Bit 4 = MSTR Master Mode This bit is set and cleared by software. It is also cleared by hardware when, in master mode, SS = 0 (see Master mode fault (MODF)). 0: Slave mode 1: Master mode. The function of the SCK pin changes from an input to an output and the functions of the MISO and MOSI pins are reversed. Bit 3 = CPOL Clock Polarity This bit is set and cleared by software. This bit determines the idle state of the serial Clock.
Serial peripheral interface (SPI) ST72361xx-Auto SPIE = 1 in the SPICR register. It is cleared by a software sequence (an access to the SPICSR register followed by a write or a read to the SPIDR register). 0: Data transfer is in progress or the flag has been cleared. 1: Data transfer between the device and an external device has been completed. Note: While the SPIF bit is set, all writes to the SPIDR register are inhibited until the SPICSR register is read.
ST72361xx-Auto 14.8.3 Serial peripheral interface (SPI) Data I/O register (SPIDR) Read/ write Reset value: Undefined 7 0 D7 D6 D5 D4 D3 D2 D1 D0 The SPIDR register is used to transmit and receive data on the serial bus. In a master device, a write to this register will initiate transmission/reception of another byte. Note: During the last clock cycle the SPIF bit is set, a copy of the received data byte in the shift register is moved to a buffer.
LINSCI serial communication interface (LIN master/slave) ST72361xx-Auto 15 LINSCI serial communication interface (LIN master/slave) 15.1 Introduction The Serial Communications Interface (SCI) offers a flexible means of full-duplex data exchange with external equipment requiring an industry standard NRZ asynchronous serial data format. The SCI offers a very wide range of baud rates using two baud rate generator systems.
ST72361xx-Auto 15.3 LINSCI serial communication interface (LIN master/slave) LIN features ● LIN master – ● 15.
LINSCI serial communication interface (LIN master/slave) ST72361xx-Auto Figure 77.
ST72361xx-Auto 15.5.2 LINSCI serial communication interface (LIN master/slave) Extended prescaler mode Two additional prescalers are available in extended prescaler mode. They are shown in Figure 79. 15.5.3 ● An extended prescaler receiver register (SCIERPR) ● An extended prescaler transmitter register (SCIETPR) Serial data format Word length may be selected as being either 8 or 9 bits by programming the M bit in the SCICR1 register (see Figure 78). The TDO pin is in low state during the start bit.
LINSCI serial communication interface (LIN master/slave) ST72361xx-Auto Character transmission During an SCI transmission, data shifts out least significant bit first on the TDO pin. In this mode, the SCIDR register consists of a buffer (TDR) between the internal bus and the transmit shift register (see Figure 77). Procedure ● Select the M bit to define the word length. ● Select the desired baud rate using the SCIBRR and the SCIETPR registers.
ST72361xx-Auto LINSCI serial communication interface (LIN master/slave) Idle line Setting the TE bit drives the SCI to send a preamble of 10 (M = 0) or 11 (M = 1) consecutive ‘1’s (idle line) before the first character. In this case, clearing and then setting the TE bit during a transmission sends a preamble (idle line) after the current word. Note that the preamble duration (10 or 11 consecutive ‘1’s depending on the M bit) does not take into account the stop bit of the previous character.
LINSCI serial communication interface (LIN master/slave) ST72361xx-Auto When an overrun error occurs: ● The OR bit is set. ● The RDR content will not be lost. ● The shift register will be overwritten. ● An interrupt is generated if the RIE bit is set and the I[|1:0] bits are cleared in the CCR register. The OR bit is reset by an access to the SCISR register followed by a SCIDR register read operation.
ST72361xx-Auto LINSCI serial communication interface (LIN master/slave) with: PR = 1, 3, 4 or 13 (see SCP[1:0] bits) TR = 1, 2, 4, 8, 16, 32, 64,128 (see SCT[2:0] bits) RR = 1, 2, 4, 8, 16, 32, 64,128 (see SCR[2:0] bits) All these bits are in the SCIBRR register. Example 1: If fCPU is 8 MHz (normal mode) and if PR = 13 and TR = RR = 1, the transmit and receive baud rates are 38400 baud. Note: The baud rate registers MUST NOT be changed while the transmitter or the receiver is enabled. 15.5.
LINSCI serial communication interface (LIN master/slave) ST72361xx-Auto Figure 79.
ST72361xx-Auto LINSCI serial communication interface (LIN master/slave) Idle line detection Receiver wakes up by idle line detection when the receive line has recognized an Idle Line. Then the RWU bit is reset by hardware but the IDLE bit is not set.
LINSCI serial communication interface (LIN master/slave) ST72361xx-Auto Example 2: data = 00110101; 4 bits set => parity bit will be 0 if even parity is selected (PS bit = 0). Odd parity The parity bit is calculated to obtain an odd number of “1s” inside the character made of the 7 or 8 LSB bits (depending on whether M is equal to 0 or 1) and the parity bit. Example 3: data = 00110101; 4 bits set => parity bit will be 1 if odd parity is selected (PS bit = 1).
ST72361xx-Auto LINSCI serial communication interface (LIN master/slave) The SCI interrupt events are connected to the same interrupt vector (see Interrupts chapter). These events generate an interrupt if the corresponding Enable Control Bit is set and the interrupt mask in the CC register is reset (RIM instruction). 15.8 SCI mode register description 15.8.
LINSCI serial communication interface (LIN master/slave) ST72361xx-Auto The OR bit is set by hardware when the word currently being received in the shift register is ready to be transferred into the RDR register whereas RDRF is still set. An interrupt is generated if RIE = 1 in the SCICR2 register. It is cleared by a software sequence (an access to the SCISR register followed by a read to the SCIDR register).
ST72361xx-Auto LINSCI serial communication interface (LIN master/slave) Bit 5 = SCID Disabled for low power consumption When this bit is set the SCI prescalers and outputs are stopped and the end of the current byte transfer in order to reduce power consumption.This bit is set and cleared by software. 0: SCI enabled 1: SCI prescaler and outputs disabled Bit 4 = M Word length. This bit determines the word length. It is set or cleared by software.
LINSCI serial communication interface (LIN master/slave) ST72361xx-Auto Bit 6 = TCIE Transmission complete interrupt enable This bit is set and cleared by software. 0: interrupt is inhibited 1: an SCI interrupt is generated whenever TC = 1 in the SCISR register Bit 5 = RIE Receiver interrupt enable. This bit is set and cleared by software. 0: interrupt is inhibited 1: an SCI interrupt is generated whenever OR = 1 or RDRF = 1 in the SCISR register Bit 4 = ILIE Idle line interrupt enable.
ST72361xx-Auto LINSCI serial communication interface (LIN master/slave) Contains the received or transmitted data character, depending on whether it is read from or written to. 7 DR7 0 DR6 DR5 DR4 DR3 DR2 DR1 DR0 The data register performs a double function (read and write) since it is composed of two registers, one for transmission (TDR) and one for reception (RDR). The TDR register provides the parallel interface between the internal bus and the output shift register (see Figure 77).
LINSCI serial communication interface (LIN master/slave) Table 64. ST72361xx-Auto Transmitter rate divider TR dividing factor SCT2 SCT1 SCT0 0 16 0 32 1 1 64 0 1 128 1 Bits 2:0 = SCR[2:0] SCI Receiver rate divider. These 3 bits, in conjunction with the SCP[1:0] bits define the total division applied to the bus clock to yield the receive rate clock in conventional Baud Rate Generator mode. Table 65.
ST72361xx-Auto 15.8.7 LINSCI serial communication interface (LIN master/slave) Extended transmit prescaler division register (SCIETPR) Read/ write Reset value: 0000 0000 (00h) 7 ETPR7 0 ETPR6 ETPR5 ETPR4 ETPR3 ETPR2 ETPR1 ETPR0 Bits 7:0 = ETPR[7:0] 8-bit Extended Transmit Prescaler Register. The extended baud rate generator is activated when a value other than 00h is stored in this register.
LINSCI serial communication interface (LIN master/slave) ST72361xx-Auto In LIN Slave mode the LIN baud rate generator is selected instead of the conventional or extended prescaler. The LIN baud rate generator is common to the transmitter and the receiver. Then the baud rate can be programmed using LPR and LPRF registers. Note: It is mandatory to set the LIN configuration first before programming LPR and LPRF, because the LIN configuration uses a different baud rate generator from the standard one. 15.9.
ST72361xx-Auto LINSCI serial communication interface (LIN master/slave) Figure 81.
LINSCI serial communication interface (LIN master/slave) Note: ST72361xx-Auto It is recommended to combine the header detection function with Mute mode. Putting the LINSCI in mute mode allows the detection of Headers only and prevents the reception of any other characters. This mode can be used to wait for the next header without being interrupted by the data bytes of the current message in case this message is not relevant for the application.
ST72361xx-Auto LINSCI serial communication interface (LIN master/slave) parity bits start bit stop bit identifier bits ID0 ID1 ID2 ID3 ID4 ID5 P0 P1 Identifier Field P0 = ID0 ID1 ID2 ID4 P1 = ID1 ID3 ID4 ID5 15.9.4 M=0 LIN error detection LIN header error flag The LIN header error flag indicates that an invalid LIN header has been detected.
LINSCI serial communication interface (LIN master/slave) ST72361xx-Auto If the LHE flag is set, it means that: D > 15.625% If LHE flag is not set, it means that: D < 16.40625% If 15.625% D 16.40625%, then the flag can be either set or reset depending on the dephasing between the signal on the RDI line and the CPU clock.
ST72361xx-Auto LINSCI serial communication interface (LIN master/slave) worst case: This occurs when the LIN identifier lasts exactly 10 TBIT_MASTER periods. In this case, the LIN break and synch fields last 49 - 10 = 39TBIT_MASTER periods. Assuming the slave measures these first 39 bits with a desynchronized clock of 15.5%. This leads to a maximum allowed header length of: 39 x (1/0.845) TBIT_MASTER + 10TBIT_MASTER = 56.
LINSCI serial communication interface (LIN master/slave) 15.9.5 ST72361xx-Auto LIN baud rate Baud rate programming is done by writing a value in the LPR prescaler or performing an automatic resynchronization as described below. Automatic resynchronization To automatically adjust the baud rate based on measurement of the LIN synch field: ● Write the nominal LIN prescaler value (usually depending on the nominal baud rate) in the LPFR / LPR registers.
ST72361xx-Auto LINSCI serial communication interface (LIN master/slave) Figure 84. LDIV read / write operations when LDUM = 0 Write LPR Write LPFR MANT(7:0) FRAC(3:0) LDIV_NOM LIN Sync Field Measurement Write LPR MANT(7:0) FRAC(3:0) LDIV_MEAS Update at end of Synch Field Baud Rate Generation MANT(7:0) FRAC(3:0) LDIV Read LPR Read LPFR Figure 85.
LINSCI serial communication interface (LIN master/slave) Note: ST72361xx-Auto If the period desynchronization of the slave is +15% (slave too slow), the character “00h” which represents a sequence of 9 low bits must not be interpreted as a break character (9 bits + 15% = 10.35). Consequently, a valid LIN Synch break must last at least 11 low bits.
ST72361xx-Auto 15.9.9 LINSCI serial communication interface (LIN master/slave) Error due to LIN synch measurement The LIN synch field is measured over eight bit times. This measurement is performed using a counter clocked by the CPU clock. The edge detections are performed using the CPU clock cycle. This leads to a precision of 2 CPU clock cycles for the measurement which lasts 16*8*LDIV clock cycles. Consequently, this error (DMEAS) is equal to: 2 / (128*LDIVMIN).
LINSCI serial communication interface (LIN master/slave) 15.10 LIN mode register description 15.10.1 Status register (SCISR) ST72361xx-Auto Read only Reset value: 1100 0000 (C0h) 7 TDRE 0 TC RDRF IDLE LHE NF FE PE Bits 7:4 = same function as in SCI mode, please refer to Section 15.8: SCI mode register description. Bit 3 = LHE LIN Header Error. During LIN header this bit signals three error types: ● The LIN synch field is corrupted and the SCI is blocked in LIN synch state (LSF bit = 1).
ST72361xx-Auto 15.10.2 LINSCI serial communication interface (LIN master/slave) Control Register 1 (SCICR1) Read/ write Reset value: x000 0000 (x0h) 7 0 R8 T8 SCID M WAKE PCE PS PIE Bits 7:3 = Same function as in SCI mode, please refer to Section 15.8: SCI mode register description. Bit 2 = PCE Parity control enable. This bit is set and cleared by software. It selects the hardware parity control for LIN identifier parity check.
LINSCI serial communication interface (LIN master/slave) 15.10.4 ST72361xx-Auto Control register 3 (SCICR3) Read/ write Reset value: 0000 0000 (00h) 7 0 LDUM LINE LSLV LASE LHDM LHIE LHDF LSF Bit 7 = LDUM LIN Divider Update Method. This bit is set and cleared by software and is also cleared by hardware (when RDRF = 1). It is only used in LIN Slave mode. It determines how the LIN Divider can be updated by software.
ST72361xx-Auto LINSCI serial communication interface (LIN master/slave) Bit 4 = LASE LIN Auto Synch Enable. This bit enables the Auto Synch Unit (ASU). It is set and cleared by software. It is only usable in LIN Slave mode. 0: auto synch unit disabled 1: auto synch unit enabled. Bit 3 = LHDM LIN Header Detection Method This bit is set and cleared by software. It is only usable in LIN Slave mode. It enables the Header Detection Method.
LINSCI serial communication interface (LIN master/slave) 15.10.5 ST72361xx-Auto LIN divider registers LDIV is coded using the two registers LPR and LPFR. In LIN slave mode, the LPR register is accessible at the address of the SCIBRR register and the LPFR register is accessible at the address of the SCIETPR register. 15.10.
ST72361xx-Auto LINSCI serial communication interface (LIN master/slave) Table 68. LDIV fraction LPFR[3:0] Fraction (LDIV) 0h 0 1h 1/16 ... ... Eh 14/16 Fh 15/16 1. When initializing LDIV, the LPFR register must be written first. Then, the write to the LPR register will effectively update LDIV and so the clock generation. 2. In LIN slave mode, if the LPR[7:0] register is equal to 00h, the transceiver and receiver input clocks are switched off.
LINSCI serial communication interface (LIN master/slave) 15.10.8 ST72361xx-Auto LIN header length register (LHLR) Read only Reset value: 0000 0000 (00h) . 7 0 LHL7 Note: LHL6 LHL5 LHL4 LHL3 LHL2 LHL1 LHL0 In LIN slave mode when LASE = 1 or LHDM = 1, the LHLR register is accessible at the address of the SCIERPR register. Otherwise this register is always read as 00h. Bits 7:0 = LHL[7:0] LIN Header Length.
ST72361xx-Auto LINSCI serial communication interface (LIN master/slave) Table 70. LHL fraction coding LHL[1:0] Fraction (57 - THEADER) 0h 0 1h 1/4 2h 1/2 3h 3/4 Example of LHL coding Example 1: LHL = 33h = 001100 11b LHL(7:3) = 1100b = 12d LHL(1:0) = 11b = 3d This leads to: Mantissa (57 - THEADER) = 12d Fraction (57 - THEADER) = 3/4 = 0.75 Therefore: (57 - THEADER) = 12.75d and THEADER = 44.25d Example 2: 57 - THEADER = 36.21d LHL(1:0) = rounded(4*0.21d) = 1d LHL(7:2) = Mantissa (36.
LINSCI serial communication interface (LIN master/slave) Table 71. Addr. (Hex.
ST72361xx-Auto LINSCI serial communication interface (LIN master only) 16 LINSCI serial communication interface (LIN master only) 16.1 Introduction The Serial Communications Interface (SCI) offers a flexible means of full-duplex data exchange with external equipment requiring an industry standard NRZ asynchronous serial data format. The SCI offers a very wide range of baud rates using two baud rate generator systems. 16.
LINSCI serial communication interface (LIN master only) 16.3 ST72361xx-Auto General description The interface is externally connected to another device by three pins (see Figure 88: SCI block diagram). Any SCI bidirectional communication requires a minimum of two pins: Receive Data In (RDI) and Transmit Data Out (TDO): ● SCLK: Transmitter Clock Output.
ST72361xx-Auto LINSCI serial communication interface (LIN master only) Figure 88.
LINSCI serial communication interface (LIN master only) ST72361xx-Auto Refer to the register descriptions in Section 15.8: SCI mode register descriptionfor the definitions of each bit. 16.4.1 Serial data format Word length may be selected as being either 8 or 9 bits by programming the M bit in the SCICR1 register (see Figure 89). The TDO pin is in low state during the start bit. The TDO pin is in high state during the stop bit.
ST72361xx-Auto LINSCI serial communication interface (LIN master only) Character transmission During an SCI transmission, data shifts out least significant bit first on the TDO pin. In this mode, the SCIDR register consists of a buffer (TDR) between the internal bus and the transmit shift register (see Figure 89). Procedure ● Select the M bit to define the word length. ● Select the desired baud rate using the SCIBRR and the SCIETPR registers.
LINSCI serial communication interface (LIN master only) ST72361xx-Auto Idle characters Setting the TE bit drives the SCI to send an idle frame before the first data frame. Clearing and then setting the TE bit during a transmission sends an idle frame after the current word. Note: Resetting and setting the TE bit causes the data in the TDR register to be lost. Therefore the best time to toggle the TE bit is when the TDRE bit is set, that is, before writing the next byte in the SCIDR.
ST72361xx-Auto LINSCI serial communication interface (LIN master only) Idle character When an idle frame is detected, there is the same procedure as a data received character plus an interrupt if the ILIE bit is set and the I bit is cleared in the CCR register. Overrun error An overrun error occurs when a character is received when RDRF has not been reset. Data cannot be transferred from the shift register to the RDR register until the RDRF bit is cleared.
LINSCI serial communication interface (LIN master only) ST72361xx-Auto Figure 90.
ST72361xx-Auto LINSCI serial communication interface (LIN master only) RR = 1, 2, 4, 8, 16, 32, 64, 128 (see SCR[2:0] bits) All these bits are in the SCIBRR register. Example 1: If fCPU is 8 MHz (normal mode) and if PR = 13 and TR = RR = 1, the transmit and receive baud rates are 38400 baud. Note: The baud rate registers MUST NOT be changed while the transmitter or the receiver is enabled. 16.4.
LINSCI serial communication interface (LIN master only) ST72361xx-Auto Receiver wakes-up by address mark detection when it received a “1” as the most significant bit of a word, thus indicating that the message is an address. The reception of this particular word wakes up the receiver, resets the RWU bit and sets the RDRF bit, which allows the receiver to receive this word normally and to use it as an address word. 16.4.
ST72361xx-Auto 16.5 LINSCI serial communication interface (LIN master only) Low power modes Table 73. Effect of low power modes on SCI Mode 16.6 Description WAIT No effect on SCI. SCI interrupts cause the device to exit from Wait mode. HALT SCI registers are frozen. In halt mode, the SCI stops transmitting/receiving until Halt mode is exited. Interrupts Table 74.
LINSCI serial communication interface (LIN master only) Note: ST72361xx-Auto The SCLK pin works in conjunction with the TDO pin. When the SCI transmitter is disabled (TE and RE = 0), the SCLK and TDO pins go into high impedance state. The LBCL, CPOL and CPHA bits have to be selected before enabling the transmitter to ensure that the clock pulses function correctly. These bits should not be changed while the transmitter is enabled. Figure 91.
ST72361xx-Auto LINSCI serial communication interface (LIN master only) Figure 93. SCI data clock timing diagram (M = 1) Idle or preceding Start transmission M = 1 (9 data bits) Stop Clock (CPOL=0, CPHA=0) Idle or next transmission * Clock (CPOL=0, CPHA=1) * Clock (CPOL=1, CPHA=0) * * Clock (CPOL=1, CPHA=1) Data 0 Start 1 2 3 4 5 6 7 8 MSB Stop LSB * LBCL bit controls last data clock pulse 16.8 Register description 16.8.
LINSCI serial communication interface (LIN master only) ST72361xx-Auto software sequence (an access to the SCISR register followed by a read to the SCIDR register). 0: data is not received 1: received data is ready to be read Bit 4 = IDLE Idle line detect. This bit is set by hardware when an Idle Line is detected. An interrupt is generated if the ILIE = 1 in the SCICR2 register. It is cleared by a software sequence (an access to the SCISR register followed by a read to the SCIDR register).
ST72361xx-Auto 16.8.2 LINSCI serial communication interface (LIN master only) Control register 1 (SCICR1) Read/ write Reset value: x000 0000 (x0h) 7 R8 0 T8 SCID M WAKE PCE PS PIE Bit 7 = R8 Receive data bit 8. This bit is used to store the 9th bit of the received word when M = 1. Bit 6 = T8 Transmit data bit 8. This bit is used to store the 9th bit of the transmitted word when M = 1.
LINSCI serial communication interface (LIN master only) 16.8.3 ST72361xx-Auto Control register 2 (SCICR2) Read/ write Reset value: 0000 0000 (00h) 7 TIE 0 TCIE RIE ILIE TE RE RWU SBK Bit 7 = TIE Transmitter interrupt enable. This bit is set and cleared by software. 0: interrupt is inhibited 1: an SCI interrupt is generated whenever TDRE = 1 in the SCISR register Bit 6 = TCIE Transmission complete interrupt enable This bit is set and cleared by software.
ST72361xx-Auto LINSCI serial communication interface (LIN master only) Bit 0 = SBK Send break. This bit set is used to send break characters. It is set and cleared by software. 0: no break character is transmitted 1: break characters are transmitted Note: If the SBK bit is set to “1” and then to “0”, the transmitter sends a BREAK word at the end of the current word. 16.8.
LINSCI serial communication interface (LIN master only) ST72361xx-Auto Bit 1 = CPHA Clock Phase. This bit allows the user to select the phase of the clock output on the SCLK pin. It works in conjunction with the CPOL bit to produce the desired clock/data relationship (see Figure 92 and Figure 93) 0: SCLK clock line activated in middle of data bit. 1: SCLK clock line activated at beginning of data bit. Bit 0 = LBCL Last bit clock pulse.
ST72361xx-Auto 16.8.6 LINSCI serial communication interface (LIN master only) Baud rate register (SCIBRR) Read/ write Reset value: 0000 0000 (00h) 7 SCP1 0 SCP0 SCT2 SCT1 SCT0 SCR2 SCR1 SCR0 Bits 7:6 = SCP[1:0] First SCI Prescaler These 2 prescaling bits allow several standard clock division ranges: Table 77.
LINSCI serial communication interface (LIN master only) Table 79. ST72361xx-Auto Receiver rate divider RR dividing factor SCR2 SCR1 SCR0 1 0 0 2 1 0 4 0 1 8 1 0 16 0 32 1 1 64 0 1 128 1 Note: This RR factor is used only when the ERPR fine tuning factor is equal to 00h; otherwise, RR is replaced by the (RR*ERPR) dividing factor. 16.8.
ST72361xx-Auto Table 80. LINSCI serial communication interface (LIN master only) Baud rate selection Conditions Symbol Parameter fCPU fTx fRx Communication frequency Table 81. Standard Accuracy vs. standard Prescaler ~0.16% Conventional Mode TR (or RR) = 128, PR = 13 TR (or RR) = 32, PR = 13 TR (or RR) = 16, PR =13 TR (or RR) = 8, PR = 13 TR (or RR) = 4, PR = 13 TR (or RR) = 16, PR = 3 TR (or RR) = 2, PR = 13 TR (or RR) = 1, PR =13 ~0.
10-bit A/D converter (ADC) ST72361xx-Auto 17 10-bit A/D converter (ADC) 17.1 Introduction The on-chip Analog to Digital Converter (ADC) peripheral is a 10-bit, successive approximation converter with internal sample and hold circuitry. This peripheral has up to 16 multiplexed analog input channels (refer to device pin out description) that allow the peripheral to convert the analog voltage levels from up to 16 different sources. The result of the conversion is stored in a 10-bit data register.
ST72361xx-Auto 10-bit A/D converter (ADC) Figure 94. ADC block diagram fCPU fADC fCPU, fCPU/2, fCPU/4 EOC SPEED ADON SLOW CH3 CH2 CH1 CH0 ADCCSR 4 AIN0 AIN1 ANALOG TO DIGITAL ANALOG MUX CONVERTER AINx ADCDRH D9 D8 ADCDRL 17.3.2 D7 0 D6 0 D5 0 D4 D3 0 0 D2 0 D1 D0 A/D conversion The analog input ports must be configured as input, no pull-up, no interrupt. Refer to the Chapter 8: I/O ports.
10-bit A/D converter (ADC) 17.3.3 ST72361xx-Auto Changing the conversion channel The application can change channels during conversion. When software modifies the CH[3:0] bits in the ADCCSR register, the current conversion is stopped, the EOC bit is cleared, and the A/D converter starts converting the newly selected channel. 17.3.
ST72361xx-Auto 10-bit A/D converter (ADC) Bit 7 = EOC End of Conversion This bit is set by hardware. It is cleared by software reading the ADCDRH register or writing to any bit of the ADCCSR register. 0: conversion is not complete 1: conversion complete Bit 6 = SPEED A/D clock selection This bit is set and cleared by software. Table 83.
10-bit A/D converter (ADC) Table 84. ST72361xx-Auto ADC channel selection (continued) Channel pin(1) CH3 CH2 CH1 CH0 0 AIN8 0 AIN9 1 0 AIN10 0 1 AIN11 1 1 AIN12 0 0 AIN13 1 1 AIN14 0 1 AIN15 1 1. The number of channels is device dependent. Refer to the device pinout description. 17.6.2 Data register (ADCDRH) Read only Reset value: 0000 0000 (00h) 7 D9 0 D8 D7 D6 D5 D4 D3 D2 Bits 7:0 = D[9:2] MSB of Analog Converted Value 17.6.
ST72361xx-Auto Instruction set 18 Instruction set 18.1 CPU addressing modes The CPU features 17 different addressing modes which can be classified in seven main groups: Table 86.
Instruction set ST72361xx-Auto Table 87. CPU addressing mode overview (continued) Mode 18.1.1 Syntax Destination Pointer address (hex.) Pointer size (hex.) Length (bytes) Short Indirect Indexed ld A, ([$10],X) 00..1FE 00..FF byte +2 Long Indirect Indexed ld A, ([$10.w], X) 0000..FFFF 00..FF word +2 Relative Direct jrne loop PC+/-127 Relative Indirect jrne [$10] PC+/-127 Bit Direct bset $10, #7 00..FF Bit Indirect bset [$10], #7 00..
ST72361xx-Auto 18.1.2 Instruction set Immediate Immediate instructions have 2 bytes, the first byte contains the opcode, the second byte contains the operand value. Immediate instruction 18.1.3 Function LD Load CP Compare BCP Bit compare AND, OR, XOR Logical operations ADC, ADD, SUB, SBC Arithmetic operations Direct In direct instructions, the operands are referenced by their memory address.
Instruction set ST72361xx-Auto The pointer address follows the opcode. The indirect addressing mode consists of two submodes: Indirect (short) The pointer address is a byte, the pointer size is a byte, thus allowing 00 - FF addressing space, and requires 1 byte after the opcode. Indirect (long) The pointer address is a byte, the pointer size is a word, thus allowing 64 Kbyte addressing space, and requires 1 byte after the opcode. 18.1.
ST72361xx-Auto Instruction set Table 89. Instructions supporting direct, indexed, indirect and indirect indexed addressing (part 2) (continued) Short instructions only 18.1.7 Function BSET, BRES Bit Operations BTJT, BTJF Bit Test and Jump Operations SLL, SRL, SRA, RLC, RRC Shift and Rotate Operations SWAP Swap Nibbles CALL, JP Call or Jump subroutine Relative mode (direct, indirect) This addressing mode is used to modify the PC register value, by adding an 8-bit signed offset to it.
Instruction set ST72361xx-Auto Table 90. Instruction groups Description 18.2.1 Instruction Shift and rotates SLL SRL SRA RLC RRC SWAP SLA Unconditional jump or call JRA JRT JRF JP CALL CALLR NOP Conditional branch JRxx Interruption management TRAP WFI HALT IRET Condition code flag modification SIM RIM SCF RCF RET Using a prebyte The instructions are described with one to four opcodes.
ST72361xx-Auto Instruction set Memo Description CALL Call subroutine CALLR Call subroutine relative CLR Function/example Clear Dst Src I1 H I0 reg, M M N Z 0 1 N Z C 1 CP Arithmetic Compare tst(Reg - M) reg CPL One Complement A = FFH-A reg, M N Z DEC Decrement dec Y reg, M N Z HALT Halt IRET Interrupt routine return Pop CC, A, X, PC N Z INC Increment inc X reg, M N Z JP Absolute Jump jp [TBL.
Instruction set Memo 226/279 ST72361xx-Auto Description NEG Negate (2's compl) NOP No Operation OR OR operation POP Pop from the Stack Function/example Dst Src neg $10 reg, M A=A+M A M pop reg reg M pop CC CC M M reg, CC I1 I1 H H I0 I0 N Z C N Z C N Z N Z C PUSH Push onto the Stack push Y RCF Reset carry flag C=0 RET Subroutine Return RIM Enable Interrupts I1:0 = 10 (level 0) RLC Rotate left true C C <= A <= C reg, M N Z C RRC Rotate right tr
ST72361xx-Auto Electrical characteristics 19 Electrical characteristics 19.1 Parameter conditions Unless otherwise specified, all voltages are referred to VSS. 19.1.1 Minimum and maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at TA = 25°C and TA = TAmax (given by the selected temperature range).
Electrical characteristics ST72361xx-Auto Figure 96. Pin input voltage ST7 PIN VIN 19.2 Absolute maximum ratings Stresses above those listed as “absolute maximum ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device under these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. 19.2.1 Voltage characteristics Symbol Ratings Maximum value VDD - VSS Supply voltage 6.
ST72361xx-Auto 19.2.
Electrical characteristics ST72361xx-Auto 19.3 Operating conditions 19.3.1 General operating conditions Symbol fCPU Parameter Conditions Internal clock frequency No Flash write/ erase. Analog parameters not guaranteed. Extended operating voltage VDD Min Max Unit 0 8 MHz 3.8 4.5 V Standard operating voltage Operating voltage for flash write/ erase 4.5 A Suffix version TA 5.5 VPP = 11.4 to 12.6V 85 Ambient temperature range -40 C Suffix version °C 125 Figure 97.
ST72361xx-Auto 19.3.3 Electrical characteristics Auxiliary voltage detector (AVD) thresholds Subject to general operating conditions for TA. Symbol Parameter Conditions Min Typ Max VIT+(AVD) 10 AVDF flag toggle threshold (VDD rise) 4.4(1) 4.6 4.9 VIT-(AVD) 01 AVDF flag toggle threshold (VDD fall) 4.2 4.4 4.65(1) Vhys(AVD) AVD voltage threshold hysteresis VIT- Voltage drop between AVD flag set and LVD reset activated Unit V VIT+(AVD)-VIT-(AVD) 250 mV VIT-(AVD)-VIT-(LVD) 450 1.
Electrical characteristics Table 91. ST72361xx-Auto Supply current consumption Flash devices Symbol Parameter Conditions ROM devices Typ (1) Max(2) Typ(1) Max(2) Supply current in RUN mode(3) fOSC = 2 MHz, fCPU = 1 MHz fOSC = 4 MHz, fCPU = 2 MHz fOSC = 8 MHz, fCPU = 4 MHz fOSC = 16 MHz, fCPU = 8 MHz 1.8 3.2 6 10 3 5 8 15 1.1 2.2 4.4 8.9 2 3.5 6 12 Supply current in SLOW mode(3) fOSC = 2 MHz, fCPU = 62.
ST72361xx-Auto Table 92. Symbol IDD(RES) Electrical characteristics Clock source current consumption Parameter Conditions Typ Unit See Section 20.5.1: Crystal and ceramic resonator oscillators Supply current of resonator oscillator(2)(3) IDD(PLL) PLL supply current VDD = 5V 360 IDD(LVD) LVD supply current HALT mode, VDD = 5V 150 1. Max(1) µA 300 Data based on characterization results, not tested in production. 2.
Electrical characteristics 19.5 ST72361xx-Auto Clock and timing characteristics Subject to general operating conditions for VDD, fOSC, and TA. Table 94. General timings Symbol Parameter tc(INST) Instruction cycle time tv(IT) Conditions fCPU = 8 MHz Interrupt reaction time(2) tv(IT) = tc(INST) + 10 fCPU = 8 MHz Min Typ(1) Max Unit 2 3 12 tCPU 250 375 1500 ns 10 22 tCPU 1.25 2.75 µs 1. Data based on typical application software. 2.
ST72361xx-Auto 19.5.1 Electrical characteristics Crystal and ceramic resonator oscillators The ST7 internal clock can be supplied with four different crystal/ ceramic resonator oscillators. All the information given in this paragraph is based on characterization results with specified typical external components. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and start-up stabilization time.
Electrical characteristics 19.5.2 ST72361xx-Auto PLL characteristics Operating conditions: VDD 3.8 to 5.5V @ TA 0 to 70°C(a) or VDD 4.5 to 5.5V @ TA -40 to 125°C Table 97. Symbol PLL characteristics Parameter Conditions VDD(PLL) PLL Voltage Range fOSC PLL input frequency range TA = 0 to +70°C 3.8 TA = -40 to +125°C 4.5 Typ Max Unit 5.5 2 fOSC = 4 MHz, VDD = 4.5 to 5.5V fCPU/fCPU PLL jitter(1) Min 4 See note(2) MHz % fOSC = 2 MHz, VDD = 4.5 to 5.5V 1.
ST72361xx-Auto 19.6 Electrical characteristics Auto wakeup from halt oscillator (AWU) Table 98. Symbol fAWU tRCSRT AWU oscillator characteristics Parameter Conditions AWU oscillator frequency(1) Min Typ Max Unit 50 100 250 kHz AWU oscillator startup time 10 µs 1. Data based on characterization results, not tested in production. Figure 102. AWU oscillator freq. @ TA 25°C Freq(KHz) 200 150 100 Ta=25C 50 4.4 5 Vdd 19.7 Memory characteristics 19.7.
Electrical characteristics ST72361xx-Auto Table 100. Dual voltage HDFlash memory (continued) Symbol Parameter Conditions Min(1) Typ Max(1) Unit tRET Data retention TA = 55°C 20 years NRW Write erase cycles TA = 85°C 100 cycles TPROG TERASE Programming or erasing temperature range -40 25 85 °C 1. Data based on characterization results, not tested in production. 2. VPP must be applied only during the programming or erasing operation and not permanently for reliability reasons. 3.
ST72361xx-Auto Electrical characteristics Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the RESET pin or the Oscillator pins for 1 second. To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note AN1015). Table 101.
Electrical characteristics ST72361xx-Auto depends on the number of supply pins in the device (3 parts*(n+1) supply pin). Two models can be simulated: human body model and machine model. This test conforms to the JESD22-A114A/A115A standard. Static and dynamic latch-up ● LU: three complementary static tests are required on 10 parts to assess the latch-up performance.
ST72361xx-Auto Electrical characteristics 19.9 I/O port pin characteristics 19.9.1 General characteristics Subject to general operating conditions for VDD, fOSC, and TA unless otherwise specified. Table 105. I/O characteristics Symbol VIL Parameter (1) Input high level voltage Vhys Schmitt trigger voltage hysteresis(2) VIH Vhys Min Typ Input low level voltage(1) VIH VIL Conditions Input low level Max 0.3 x VDD CMOS ports 0.
Electrical characteristics ST72361xx-Auto Figure 103. Connecting unused I/O pins VDD ST72XXX 10k UNUSED I/O PORT UNUSED I/O PORT 10k ST72XXX Figure 104. RPU vs VDD with VIN = VSS 200 Ta=-45C Ta=25C Ta=130C Rpu (Ko) 150 100 50 0 3.5 4 4.5 5 5.5 Vdd Figure 105. IPU vs VDD with VIN = VSS Ta=-45C Ta=25C Ta=130C Ipu (µA) 100 80 60 40 20 0 3.5 242/279 4 4.5 Vdd Doc ID 12468 Rev 3 5 5.
ST72361xx-Auto Output driving current Subject to general operating conditions for VDD, fOSC, and TA unless otherwise specified. Table 106. Output driving current VOL(1) VOH (2) Parameter Conditions Min Max Output low level voltage for a standard I/O pin when eight pins are sunk at same time (see Figure 129) IIO = +5 mA 1.2 IIO = +2 mA 0.
Electrical characteristics ST72361xx-Auto Figure 108. Typical VOH at VDD = 5V 4.9 4.8 4.7 Voh(V) 4.6 4.5 4.4 -45°C 4.3 130°C 25°C 4.2 4.1 -2 -5 Iio(mA) Figure 109. Typical VOL vs VDD (standard I/Os) 1.1 0.4 -45°C 1 0.9 25°C 130°C 0.8 Vol(V) Iio=2mA Vol(V) Iio=5mA -45°C 0.35 25°C 0.7 0.6 130°C 0.3 0.25 0.2 0.5 0.15 0.4 0.3 0.1 3 4 5 6 3 4 Vdd(V) 5 6 Vdd(V) Figure 110. Typical VOL vs VDD (high-sink I/Os) 0.4 1.3 0.3 1.2 25°C 1.
ST72361xx-Auto Electrical characteristics Figure 111. Typical VOH vs VDD 6 6 -45°C 5 130°C Voh(V) Iio=5mA Voh(V) Iio=2mA 25°C 5 -45°C 4 25°C 4 3 130°C 3 2 2 1 3 4 5 6 3 4 Vdd(V) 5 6 Vdd(V) 19.10 Control pin characteristics 19.10.1 Asynchronous RESET pin Subject to general operating conditions for VDD, fOSC, and TA unless otherwise specified. Table 107.
Electrical characteristics ST72361xx-Auto RESET circuit design recommendations The reset network protects the device against parasitic resets. The output of the external reset circuit must have an open-drain output to drive the ST7 reset pad. Otherwise the device can be damaged when the ST7 generates an internal reset (LVD or watchdog). Whatever the reset source is (internal or external), the user must ensure that the level on the RESET pin can go below the VIL max. level specified in Section 20.10.
ST72361xx-Auto Electrical characteristics Tips when using the LVD 1. Check that all recommendations related to reset circuit have been applied (see RESET circuit design recommendations) 2. Check that the power supply is properly decoupled (100nF + 10µF close to the MCU). Refer to AN1709. If this cannot be done, it is recommended to put a 100 nF + 1M pulldown on the RESET pin. 3. The capacitors connected on the RESET pin and also the power supply are key to avoiding any start-up marginality.
Electrical characteristics 19.11 ST72361xx-Auto Timer peripheral characteristics Subject to general operating conditions for VDD, fOSC, and TA unless otherwise specified. Refer to I/O port characteristics for more details on the input/output alternate function characteristics (output compare, input capture, external clock, PWM output...). Table 109.
ST72361xx-Auto Electrical characteristics Table 111. 16-bit timer characteristics (continued) Symbol tCOUNTER Parameter Conditions Timer clock period when internal clock is selected fCPU = 8 MHz Doc ID 12468 Rev 3 Min Typ Max Unit 2 8 tCPU 0.
Electrical characteristics ST72361xx-Auto 19.12 Communication interface characteristics 19.12.1 SPI - serial peripheral interface Subject to general operating conditions for VDD, fOSC, and TA unless otherwise specified. Refer to I/O port characteristics for more details on the input/output alternate function characteristics (SS, SCK, MOSI, MISO). Table 112. SPI characteristics Symbol Parameter fSCK = 1 / tc(SCK) SPI clock frequency tr(SCK) fCPU / 128 = 0.
ST72361xx-Auto Electrical characteristics Figure 116. SPI slave timing diagram with CPHA = 0 SS INPUT SCK INPUT tsu(SS) tc(SCK) th(SS) CPHA = 0 CPOL = 0 CPHA = 0 CPOL = 1 tw(SCKH) tw(SCKL) ta(SO) MISO OUTPUT tv(SO) MSB OUT See note 2 tsu(SI) th(SO) BIT6 OUT tdis(SO) tr(SCK) tf(SCK) LSB OUT See note 2 th(SI) MSB IN MOSI INPUT LSB IN BIT1 IN 1. Measurement points are done at CMOS levels: 0.3 x VDD and 0.7 x VDD 2.
Electrical characteristics ST72361xx-Auto Figure 118. SPI master timing diagram SS INPUT tc(SCK) CPHA = 0 CPOL = 0 SCK INPUT CPHA = 0 CPOL = 1 CPHA = 1 CPOL = 0 CPHA = 1 CPOL = 1 tw(SCKH) tw(SCKL) tsu(MI) MISO INPUT tr(SCK) tf(SCK) th(MI) MSB IN BIT6 IN tv(MO) MOSI OUTPUT See note 2 MSB OUT LSB IN th(MO) LSB OUT BIT6 OUT See note 2 1. Measurement points are done at CMOS levels: 0.3 x VDD and 0.7 x VDD. 2.
ST72361xx-Auto Electrical characteristics 1. Data based on characterization results, not tested in production. 2. When VDDA and VSSA pins are not available on the pinout, the ADC refers to VDD and VSS. Figure 119. RAIN max vs fADC with CAIN = 0pF 45 Max. R AIN (Kohm) 40 4 MHz 35 2 MHz 30 1 MHz 25 20 15 10 5 0 0 10 30 70 CPARASITIC (pF) 1. CPARASITIC represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the pad capacitance (3pF).
Electrical characteristics ST72361xx-Auto Analog power supply and reference pins Depending on the MCU pin count, the package may feature separate VDDA and VSSA analog power supply pins. These pins supply power to the A/D converter cell and function as the high and low reference voltages for the conversion. In smaller packages VDDA and VSSA pins are not available and the analog supply and reference pads are internally bonded to the VDD and VSS pins.
ST72361xx-Auto Electrical characteristics ADC accuracy Table 114. ADC accuracy with fCPU = 8 MHz, fADC = 4 MHz RAIN < 10kW, VDD = 5V Symbol Parameter |ET| Total unadjusted error(1) |EO| Offset error(1) |EG| Conditions Typ Max 4 Note(2) Unit 2.5 4 (1) Gain error 3 LSB (1) |ED| Differential linearity error |EL| Integral linearity error(1) 1.5 2 1. Data based on characterization results, not tested in production. ADC accuracy vs.
Electrical characteristics ST72361xx-Auto Figure 123. ADC accuracy (1) Example of an actual transfer curve Digital Result ADCDR EG 1023 1022 1021 1LSB IDEAL (3) End point correlation line V –V DDA SSA = ----------------------------------------- ET=Total Unadjusted Error: maximum deviation between the actual and the ideal transfer curves. 1024 (2) ET (1) 6 4 EO=Offset Error: deviation between the first actual transition and the first ideal one.
ST72361xx-Auto Package characteristics 20 Package characteristics 20.1 ECOPACK® In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. 20.2 Package mechanical data Figure 124. 32-pin low profile quad flat package (7x7) inches(1) mm Dim.
Package characteristics ST72361xx-Auto Figure 125. 44-pin low profile quad flat package (10x10) inches(1) mm Dim. Min Typ A A A2 D D1 A1 b e L Typ 0.15 A1 0.05 0.002 A2 1.35 1.40 1.45 0.053 0.055 0.057 b 0.30 0.37 0.45 0.012 0.015 0.018 C 0.09 0.20 0.004 0.000 0.008 12.00 0.006 0.472 10.00 0.394 E 12.00 0.472 E1 10.00 0.394 e 0.80 0.031 h Max 0.063 D1 c L1 Min 1.60 D E1 E Max q 0° 3.5° 7° 0° 3.5° 7° L 0.45 0.60 0.75 0.018 0.024 0.
ST72361xx-Auto 20.3 Package characteristics Thermal characteristics Symbol Ratings RthJA PD Value Unit Package thermal resistance (junction to ambient) LQFP64 LQFP44 LQFP32 60 52 70 °C/W Power dissipation(1) 500 mW 150 °C (2) TJmax Maximum junction temperature 1. The maximum power dissipation is obtained from the formula PD = (TJ - TA) / RthJA.
Device configuration and ordering information ST72361xx-Auto 21 Device configuration and ordering information 21.1 Introduction Each device is available for production in user programmable versions (Flash) as well as in factory coded versions (ROM/FASTROM). ST72361-Auto devices are ROM versions. ST72P361-Auto devices are Factory Advanced Service Technique ROM (FASTROM) versions: They are factory-programmed HDFlash devices.
ST72361xx-Auto Caution: Device configuration and ordering information The PLL can be enabled only if the “OSC RANGE” (OPT11:10) bits are configured to “MP 2~4 MHz”. Otherwise, the device functionality is not guaranteed. Static option byte 0 1 1 1 1 1 1 1 0 1 0 1 0 1 0 RSTC 1 1 0 7 Reserved Default(1) PKG FMP_R Reserved LVD WDG PLLOFF SW 0 HALT 7 Static option byte 1 1 1 1 0 1 1 1 1 AFI_MAP OSCTYPE OSCRANGE 1. Option bit values programmed by ST.
Device configuration and ordering information ST72361xx-Auto Table 116. Alternate function remapping 1 AFI mapping 1 AFI_MAP(1) T16_OCMP1 on PD3 T16_OCMP2 on PD5 T16_ICAP1 on PD4 LINSCI2_SCK not available LINSCI2_TDO not available LINSCI2_RDI not available 0 T16_OCMP1 on PB6 T16_OCMP2 on PB7 T16_ICAP1 on PC0 LINSCI2_SCK on PD3 LINSCI2_TDO on PD5 LINSCI2_RDI on PD4 1 Table 117.
ST72361xx-Auto Device configuration and ordering information Table 119. OSCRANGE selection (continued) OSCRANGE Typical frequency range 1 MS 4~8 MHz 0 0 1 HS 8~16 MHz 1 OPT1 = reserved OPT0 = RSTC RESET clock cycle selection This option bit selects the number of CPU cycles inserted during the RESET phase and when exiting HALT mode. For resonator oscillators, it is advised to select 4096 due to the long crystal stabilization time.
Device configuration and ordering information 21.2.2 ST72361xx-Auto Flash ordering information The following Figure 152 serves as a guide for ordering. Figure 128.
ST72361xx-Auto 21.3 Device configuration and ordering information Transfer of customer code Customer code is made up of the ROM/FASTROM contents and the list of the selected options (if any). The ROM/FASTROM contents are to be sent on diskette, or by electronic means, with the S19 hexadecimal file generated by the development tool. All unused bytes must be set to FFh. The selected options are communicated to STMicroelectronics using the correctly completed OPTION LIST appended.
Device configuration and ordering information ST72361xx-Auto Figure 130. ST72361xx-Auto ROM commercial product structure Example: ST72 361 T A /xxx Product class ST72 microcontroller Sub-family type 361 = 361 sub-family Package type T = LQFP Temperature range A = -40 °C to 85 °C C = -40 °C to 125 °C Code name Defined by STMicroelectronics. Denotes ROM code, pinout and program memory size.
ST72361xx-Auto Device configuration and ordering information ST72361-Auto MICROCONTROLLER OPTION LIST (Last update: March 2008) Customer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Address .................................................................. .................................................................. Contact .................................................................. Phone No . . . . . . . .
Development tools 22 ST72361xx-Auto Development tools Full details of tools available for the ST7 from third party manufacturers can be obtained from the STMicroelectronics Internet site: www.st.com. Tools from isystem and hitex include C compliers, emulators and gang programmers. Note: Before designing the board layout, it is recommended to check the overall dimensions of the socket as they may be greater than the dimensions of the device.
ST72361xx-Auto Important notes 23 Important notes 23.1 All devices 23.1.1 RESET pin protection with LVD enabled As mentioned in note 2 below Figure 135, when the LVD is enabled, it is recommended not to connect a pull-up resistor or capacitor. A 10nF pull-down capacitor is required to filter noise on the reset line. 23.1.
Important notes ST72361xx-Auto If these conditions are not met, the symptom can be avoided by implementing the following sequence: PUSH CC SIM reset flag or interrupt mask POP CC 23.1.3 External interrupt missed To avoid any risk of generating a parasitic interrupt, the edge detector is automatically disabled for one clock cycle during an access to either DDR and OR. Any input signal edge during this period will not be detected and will not generate an interrupt.
ST72361xx-Auto Important notes LD A, PFDR AND A, #02 LD Y, A; store the level after writing to PxOR/PxDDR LD A, X; check for falling edge cp A, #02 jrne OUT TNZ Y jrne OUT LD A, sema; check the semaphore status if edge is detected CP A, #01 jrne OUT call call_routine; call the interrupt routine OUT:LD A,#00 LD sema, A .call_routine; entry to call_routine PUSH A PUSH X PUSH CC .
Important notes ST72361xx-Auto PUSH CC .ext1_rt; entry to interrupt routine LD A, #$00 LD sema, A IRET 23.1.4 Unexpected reset fetch If an interrupt request occurs while a "POP CC" instruction is executed, the interrupt controller does not recognize the source of the interrupt and, by default, passes the RESET vector address to the CPU. Workaround To solve this issue, a "POP CC" instruction must always be preceded by a "SIM" instruction. 23.1.
ST72361xx-Auto Important notes Figure 131. Header reception event sequence LIN Synch Break LIN Synch Field Identifier Field THEADER ID field STOP bit Critical Window Active mode is set (RWU is cleared) RDRF flag is set Figure 132.
Important notes ST72361xx-Auto Occurrence The occurrence of the problem is random and proportional to the baud rate. With a transmit frequency of 19200 baud (fCPU = 8 MHz and SCIBRR = 0xC9), the wrong break duration occurrence is around 1%. Workaround If this wrong duration is not compliant with the communication protocol in the application, software can request that an Idle line be generated before the break character.
ST72361xx-Auto 23.2.2 Important notes 16-bit and 8-bit timer PWM mode In PWM mode, the first PWM pulse is missed after writing the value FFFCh in the OC1R or OC2R register. 23.3 ROM devices only 23.3.1 16-bit timer PWM mode buffering feature change In all devices, the frequency and period of the PWM signal are controlled by comparing the counter with a 16-bit buffer updated by the OCiHR and OCiLR registers.
Revision history 24 276/279 ST72361xx-Auto Revision history Doc ID 12468 Rev 3
ST72361xx-Auto Revision history Table 120. Document revision history Date 19-Sep-2006 Revision 1 Changes Initial release of ST72361-Auto datasheet (derived from ST72361 datasheet, initially released as Rev.
Revision history ST72361xx-Auto Table 120.
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