Datasheet

FS98O22
Rev. 1.6 98/146
Table 9-2 I2C register table
Address Name
Referenced
Section
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on
Power on
Reset
06H INTF 3/6/7/9/10/11 -- I2CIF -- -- -- 00000000
07H INTE 3/6/7/9/10/11 GIE -- I2CIE -- -- -- 00000000
37H PT2OCB 9 PT2OC[4:3] uuu11uuu
57H I2CCON 9 WCOL I2COV I2CEN CKP 0001uuuu
58H I2CSTA 9 DA P S RW BF uu0000u0
59H I2CADD 9 I2CADD [7:0] 00000000
5AH I2CBUF 9 I2CBUF [7:0] 00000000
I2C data receive operation: (master to slave)
1. Configure SCL and SDA pins as open-drain through the PTOCB[4:3]
2. Set I2CEN register flag to enable the I2C module.
3. Clear I2CIF to reset the I2C interrupt.
4. Set I2CIE and GIE to enable the I2C interrupt.
5. Wait for the interrupt.
6. When the I2C master device sends data to slave side, the data (ID) transmitted from the master device
will be sent to I2CBUF, and the BF register flag will be set.
7. If the RW register flag is set, the I2C module will enter the receive mode.
8. The acknowledgement signal will be sent automatically and an interrupt will occur.
9. Clear the I2CIF and reset the interrupt to wait for the interrupt happened again.
10. When an interrupt occurs, read the I2CBUF for receiving the data transmitted from master side. The
acknowledgement signal will be sent automatically.
11. If the user doesn’t read the data from I2CBUF, the BF register flag will be held high. When the data is sent
to slave again, the I2COV register flag will be set, and the interrupt will NOT happen.
Figure 9-3 I2C waveform for reception
FORTUNE'
Properties
For Reference Only