Datasheet

FS98O22
Rev. 1.6 88/146
Table 8-1 PDM module register table
Address Name
Referenced
Section
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on Power on
Reset
27H PT2MR 7.2/7.5/8 -- PM1EN -- -- 00000000
30H PMD1H 8 PMD1[15:8] 00000000
31H PMD1L 8 PMD1[7:0] 00000000
32H PMD2H PDMD2[15:8] 00000000
33H PMD2L PDMD2[7:0] 00000000
36H PMCON 8 PDMEN PMCS[2:0] 00000000
Register PT2MR at address 27H
property U-0 U-0 U-0 R/W-0 U-0 U-0 U-0 U-0
PT2MR
-- PM2EN PM1EN -- --
Bit7 Bit0
Bit 6 PM1EN: PT2[5] output multiplexer (Please refer to Section 7.3 for details)
1 = GPIO Port 2 bit 5 (PT2[5]) is defined as PDM output.
0 = GPIO Port 2 bit 5 (PT2[5]) is defined as GPIO.
Bit 4 PM1EN: PT2[2] output multiplexer (Please refer to Section 7.3 for details)
1 = GPIO Port 2 bit 2 (PT2[2]) is defined as PDM output.
0 = GPIO Port 2 bit 2 (PT2[2]) is defined as GPIO.
Property
R = Readable bit W = Writable bit U = unimplemented bit
- n = Value at Power On
Reset
‘1’ = Bit is Set ‘0’ = Bit is Cleared X = Bit is unknown
FORTUNE'
Properties
For Reference Only