Datasheet

FS98O22

Rev. 1.6 86/146

8. PDM (Pulse Density Modulator) Module

Please see Figure 8-1 and Figure 8-2. The GPIO port 2 bit 2 (PT2[2]) could be defined as either PDM module

output or General purpose I/O. User could control the PDMEN register flags to decide the definition. The PDM

module is the function FS98O22 uses for implementing the PWM (Pulse Width Modulation). Its working

flowchart and usage will be described in this Chapter. First of all, a user needs to setup the PMCS register flag

to decide the PDM CLK which is generated by a Frequency divider from the MCK

. Then, the PDM CLK will be

divided into 16 internal clock signals named PDM15, PDM14,…, PDM0. Finally, the user should control the

PMD1 (PMD1H and PMD1L) register flag to do the combination of these 16 internal clock signals. For example,

if the PMD1 is set as 0x1228H, the output signal is assigned to be the combination of PDM12, PDM9, PDM5

and PDM3. If the PMD1 is set as 0x6000H, the output signal is assigned to be the combination of PDM14 and

PDM13 (please refer to the following figure).The PMD1 value could be assigned from 0 to 65535, and the

output signal duty cycle could be from 0 to 65535/65536

. For example, when user sets the PMD1 as 0x6000H

(24576), the equivalent PWM duty cycle is 24576/65536.

Figure 8-1 FS98O22 PDM module function block

Please refer to Chapter 5 for MCK detailed information.

The PDM couldn’t generate signal as duty cycle 1, user needs to define the port as General purpose I/O

and keep it at high voltage level (data 1) manually to represent Duty Cycle 1.

FORTUNE'

Properties

For Reference Only