Datasheet

FS98O22
Rev. 1.6 81/146
z Input:
GPIO Port 2 Bit4 and Bit3 (PT2[4:3]) could be the I2C Module SCL and SDA ports or be the general I/O
ports. User should setup I2CEN register flag to decide the I2C Module is enabled or not. The detailed I2C
Module usage is described in Chapter 9.
The input port has a Schmitt trigger in it, and the up/down trigger voltage level is 0.45VDD/0.2VDD.
z Output
FS98O22 sends the digital data out by an embedded D Flip Flop. When the program sends data out
through PT2, the data will be sent to data bus first, and then the D Flip Flop will latch the signal for PT2
output while the Write signal and AR (FS98O22 internal device address pointer) is pointed to PT2.
z Pull up resistor
FS98O22 embeds an internal pull up resistor function in PT2 with about 1000k ohm resistor
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. User could
control the PT2PU[4:3] register flags to decide the connections to pull up resistor. When a port is
connected to the pull up resistor, the input data is, by default, assigned to high (data 1).
z Open Drain Control
FS98O22 embeds an internal Open Drain Control function in PT2[4:3]. Users could control the
PT2OC[4:3] register flags to decide if the Open Drain Control function is enabled. When the user assigns
these 2 ports to be SCL and SDA, PT2OC[4:3] should be set. Please refer to Chapter 9.
Table 7-5 PT2 register table
Address Name
Referenced
Section
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on Power on
Reset
24H PT2 7 PT2 [7:0] uuuuuuuu
25H PT2EN 7 PT2EN [7:0] 00000000
26H PT2PU 7 PT2PU [7:0] 00000000
37H PT2OC
B
9 PT2OC[4:3]
uuu11uuu
Read data Operation
1. Clear the PT2EN[n]
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register flags. The PT2[n] will be defined as an input port.
2. Set the PT2PU[n] register as required. The PT2[n] will be connected to an internal pull up resistor.
3. Set the PT2OC[n] register as required. The PT2[n] will be connected to an internal pull low resistor.
4. After the signal input from outside, user could get the data through PT2[n]
Write data Operation
1. Set the PT2EN[n] register flags. The PT2[n] will be defined as an output port.
2. Set the PT2PU[n] register as required. The PT2[n] will be connected to an internal pull up resistor.
3. Set the PT2OC[n] register as required. The PT2[n] will be connected to an internal pull low resistor.
4. Set the PT2[n] to output the data. The embedded D Flip Flop will latch the data till PT2[n] is changed.
Notice Operation
1. Parallel a small resistor (about 10k ohm) between ports and VDD to enlarge the possible output current
when the PT2PU[n] is set.
2. The Pull up resistor function and the Open drain control function should NOT be enabled at the same
time.
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The pull up current is about 10uA. Remember to disable PT1PU before program falls into Sleep mode.
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n means the bit index that a user want to control
FORTUNE'
Properties
For Reference Only