Datasheet

FS98O22
Rev. 1.6 76/146
Table 7-2 PT1 register table
Address Name
Detail on
Chapter
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on Power on
Reset
20H PT1 7 PT1 [7:0] uuuuuuuu
21H PT1EN 7 PT1EN [7:0] 00000000
22H PT1PU 7 PT1PU [7:0] 00000000
23H AIENB1 7 AIENB[7:6] AIENB[5:0] 00000000
Read data Operation
1. Clear the PT1EN[n]
10
register flags. The PT1[n] will be defined as an input port.
2. Set the PT1PU[n] register as required. The PT1[n] will be connected to an internal pull up resistor.
3. Set the AIENB[n] register flags if the input signals are analog signals.(n = 7 to 0)
4. Clear the AIENB[n] register flags if the input signals are analog signals. (n = 7 to 0
11
)
5. The VDDA Regulator must be enabled first, and then the AIN0~AIN7 can work correctly. (Please refer to
Chapter 4)
6. After the signal input from outside, users can get the data through PT1[n]
Write data Operation
1. Set the PT1EN[n] register flags. The PT1[n] will be defined as an output port.
2. Set the PT1PU[n] register as required. The PT1[n] will be connected to an internal pull up resistor.
3. Set the PT1[n] to output the data. The embedded D Flip Flop will latch the data till PT1[n] is changed.
Notice Operation
1. To keep low operation current in SLEEP mode, set AIENB[7:0] to let the PT1 be floating.
2. Parallel a small resistor (about 10k ohm) between ports and VDD to increase the possible output current
when the PT1PU[n] is set.
10
n means the bits indexes user want to control
11
PT1 bit6 and bit7 could only be defined as digital signal input.
FORTUNE'
Properties
For Reference Only