Datasheet

FS98O22
Rev. 1.6 57/146
6.2. Watch Dog Timer
8 bits Counter1
Watch Dog
Timer
Oscillator
WDTEN
Multiplex
WDTA[7:0]
WDTS[2:0]
8 bits Counter2
WDTOUT
CLRWDT
Figure 6-2 watch dog timer function block
Please see Figure 6-2. WDT (Watch Dog Timer) is used to prevent the program from being out of control by any
uncertain reason. When WDT is active, it will reset the CPU when the WDT timeout. Generally, the program run
in FS98O22 needs to reset the WDT before the WDT times out every time to reset the CPU. When some
trouble happens, the program will be reset to the general situation by WDT and the program won’t reset the
WDT in that situation.
The input of Watch Dog Timer is WDTEN and WDTS[2:0] register flags. The output of Watch Dog Timer is TO
register flag. When a user sets the WDTEN, the embedded Watch Dog Timer Oscillator (3 KHZ) will become
active, and the generated clock will be pushed into the “8-bit counter 1” as shown in Figure 6-2. The output of
the “8-bit counter 1”, WDTA[7:0], is a virtual signal which is sent to one multiplexer. The multiplexer is controlled
by the register flags, WDTS[2:0]. The output signal is used as the “8-bit Counter 2” clock input. When “8-bit
Counter 2” overflows, it will send WDTOUT to reset the CPU (Program Counter will jump to 0x00H to reset the
program) and set TO flag. Users could reset the WDT by the instruction – CLRWDT.
Table 6-9 watch dog timer register table
Address Name
Referenced
Section
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on Power on Reset
04H STAT
US
1.11/3.4.2 -- TO -- -- --
00u00uuu
0DH WDT
CON
6.3 WDTEN WDTS [2:0]
0uuuu000
Operation:
1. Setup the WDTS[2:0] to decide the WDT timeout frequency.
2. Set WDTEN register flag to enable the WDT.
3. Process the CLRWDT instruction to reset the WDT in the program.
FORTUNE'
Properties
For Reference Only