Datasheet

FS98O22
Rev. 1.6 18/146
1.12. Clocking Scheme/Instruction Cycle
One Instruction cycle (CPU cycle) includes 4 steps and the CPU could process 2 steps per CPU Clock. Users
can setup the MCK Register to decide the step timing. Please refer to Chapter 5 for related information. For
Example, if the MCK Register is filled with 0x04h (MCK = ICK, Instruction Cycle = MCK / 2, ICK = 1MHZ), the
step timing is 500k HZ, and one instruction cycle needs 4us (2 x 1/500k sec) to complete. The 4 steps are
described as follows. Please refer to the CPU core (Section 1.11) to understand these 4 steps.
1. Fetch
Program Counter pushes the Instruction Pointer into Program Memory, and the pointed Data in the
Program Memory is stored in the Instruction Register.
2. Decode
The Instruction Register pushes the Direct Address to Address MUX, or pushes the Direct Data to Data
MUX, and pushes the Control Information into Instruction Decoder to decode the OPCODE.
3. Execute
ALU executes the process based on the decoded Control Information.
4. Write Back
Push the ALU result to Work Register or Assigned Data Memory Address.
Because one OPCODE can only have either Direct Address or Direct Data, sometimes user needs 2
instructions to complete one simple job. For example, if user want to fill Data Memory address 0x55h with data
0xFFh, user needs to process 【movlw 0xFFh】 to filled Work Register with 0xFFh, and then process 【movwf
0x55h】to fill Data Memory 0x55h with Work Register content. For the same reason, CPU needs 2 instruction
cycles to complete some kinds of instructions such as call, goto…etc. Please see the Figure 1-4.
Figure 1-4 FS98O22 instruction cycle
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