Datasheet

FS98O22
Rev. 1.6 116/146
To get a correct ADC result, Doff(ADC input offset digital output) should be deducted from the Dout. The
instruction is as follows:
1. Set AZ bit, and VIH and VIL will short. Dout will be 15625 *G * (Vio) / (VRH-VRL+Vro). It’s called Doff.
2. Save Doff in memory, and then Clear AZ bit to restart the ADC module.
3. Pass the first 2 ADC interrupts for ignoring the unstable ADC result.
4. When measuring analog signal, Doff should be deducted.
11.5. ADC Digital Output
The ADC digital output deducted by Doff is ADC Gain. The ADC Gain doesn’t change as VDD changes. The
suggested values for common mode voltages at ADC input and reference voltage are 1V~2V.
ADC input gain could be set by ADG[1:0] register flag. Please see Section 10.1 for detail.
11.6. ADC Resolution
ADC resolution is mainly affected by the ADC sampling counts and the ADC reference voltage. Generally
speaking, the more times ADC samples the analog input signal, the more precise the digital output is. The ADC
sampling counts could be decided by ADM[2:0] register flag. The ADC digital output rolling counts versus
ADM[2:0] and Reference voltage table are shown as follows:
z (VRH, VRL) =0.4V, (VIH, VIL) =0.2V, VRL=VIL=AGND. G=1
Table 11-1 ADC rolling counts versus ADM
ADM 000 001 010 011 100 101 110
Rolling counts 10 6 4 3 3 2 1
z (VRH, VRL) =VR, (VIH, VIL) =1/2 VR, VRL=VIL=AGND. G=1 ADM=101
Table 11-2 ADC rolling counts versus VR
VR 0.05 0.1 0.2 0.3 0.4 0.6 0.8 1.0
Rolling counts 31 15 5 3 2 2 4 9
FORTUNE'
Properties
For Reference Only