Datasheet

FS98O22
Rev. 1.6 111/146
Table 10-5 INH selection table
SFTA[1:0] INH (ADC positive input port signal)
00 FTB
01 FTIN
10 AIN2
11 AIN3
5. Set SINL[1:0] to decide the ADC negative input port signal. (Table 10-6)
Table 10-6 INL selection table
SINL[1:0] INL (ADC negative input port signal)
00 AIN1
01 AIN2
10 AIN3
11 TEMPL
6. Set ADG[1:0] to decide the ADC input gain. (Table 10-7)
Table 10-7 ADG selection table
ADG[1:0]
A
DC input gain
00 2/3
01 1
10 2
11 7/3
7. Set SREFO register flag to enable the VR1P and VR2P if needed. (VR1P = 2/5 REFO, VR2P = 1/5
REFO)
8. Set SVRH[1:0] to decide the ADC reference voltage positive input port signal. (Table 10-8)
Table 10-8 VRH selection table
SVRH[1:0]
V
RH (ADC reference voltage positive input)
00 AIN0
01 AIN3
10 VR1P
11 VR2P
9. Set SVRL[1:0] to decide the ADC reference voltage negative input port signal. (Table 10-9)
FORTUNE'
Properties
For Reference Only