Datasheet

FS98O22
Rev. 1.6 110/146
Table 10-2 ADC function register table
Address Name
Referenced
Section
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on Power on
Reset
06H INTF 3/6/7/9/10/1
1
-- -- ADIF -- --
00000000
07H INTE 3/6/7/9/10/1
1
GIE -- -- ADIE -- --
00000000
10H ADOH 10/11 ADO [15:8] 00000000
11H ADOL 10/11 ADO [7:0] 00000000
13H ADCON 10/11 ADRST ADM [2:0] uuuu0000
14H MCK 5 -- -- -- -- -- -- M1_CK -- 00000000
18H NETA 10/11 SINL[1:0] SINH[2:0] SFTA[2:0] 00000000
19H NETB 10/11 -- SVRL[1:0] SVRH[1:0] 00000000
1AH NETC 10/11 SREFO ADG[1:0] ADEN AZ 00000000
ADC Operation
1. Operate as in Section 4.1 to get the VGG (2 times VDD or external Power Supply).
2. Operate as in Section 4.2 to get the VDDA (3.6V)
3. Operate as in Section 4.3 to enable the Analog Bias Circuit
4. Set SINH[2:0] and SFTA[2:0] to decide the ADC positive input port signal.(Table 10-3, 10-4 and 10-5)
Table 10-3 FTIN selection table
SINH[2:0] FTIN
000 OP1O
001 OP1P
010 VRH
011 VRL
100 TEMPH
101 AIN5
110 AIN4
111 AGND
Table 10-4 FTB selection table
SFTA[2] FTB
27
0
ADC Low Pass Filter is disabled
1
ADC Low Pass Filter is enabled
27
The input of ADC Low Pass Filter is FTIN, and the output is FTB
FORTUNE'
Properties
For Reference Only