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REV. 1.6 FS98O22-DS-16_EN MAY 2014

Datasheet

FS98O22

8-bit MCU with 4k program EPROM, 256-byte RAM,

1 low noise OPAMP, 8-ch 14-bit ADC,

4 × 20 LCD driver and RTC

FORTUNE'

Properties

For Reference Only

Summary of content (146 pages)

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FS98O22-DS-16_EN MAY 2014 FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y REV. 1.
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FS98O22 FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y Fortune Semiconductor Corporation 富晶電子股份有限公司 23F., No.29-5,Sec. 2, Zhongzheng E. Rd., Danshui Dist, New Taipei City 251, Taiwan Tel.：886-2-28094742 Fax：886-2-28094874 www.ic-fortune.com This manual contains new product information. Fortune Semiconductor Corporation reserves the rights to modify the product specification without further notice. No liability is assumed by Fortune Semiconductor Corporation as a result of the use of this product.
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FS98O22 Contents DEVICE OVERVIEW ....................................................................................................................................................... 10 1.1 High Performance RISC CPU ..................................................................................................... 10 1.2 Peripheral Features..................................................................................................................... 10 1.3 Analog Features .................
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FS98O22 4.6 CLOCK SYSTEM............................................................................................................................................................ 40 5.1 Oscillator State ............................................................................................................................ 41 5.2 CPU Instruction Cycle ................................................................................................................ 42 5.3 ADC Sample Frequency ....
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FS98O22 12.2 Differential Amplifier ................................................................................................................. 118 13. LCD DRIVER ................................................................................................................................................................ 119 14. HALT AND SLEEP MODES ......................................................................................................................................... 131 15.
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FS98O22 Figure List FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y Figure 1-1 FS98O22 pin configuration ......................................................................................... 12 Figure 1-2 FS98O22 function block .............................................................................................. 14 Figure 1-3 FS98O22 CPU core function block ............................................................................. 16 Figure 1-4 FS98O22 instruction cycle ............
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FS98O22 Table List FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y Table 1-1 Ordering Information ...................................................................................................... 11 Table 1-2 FS98O22 pin description ............................................................................................... 13 Table 1-3 FS98O22 main function description table ...................................................................
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FS98O22 FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y Table 8-1 PDM module register table ............................................................................................ 88 Table 8-2 PMD register table ......................................................................................................... 92 Table 8-3 PDM CLK selection table ............................................................................................... 92 Table 9-1 I2C module register table .........
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FS98O22 Register List FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y Register STATUS at address 04H ................................................................................................. 24 Register INTE at address 07H ....................................................................................................... 25 Register INTF at address 06H ....................................................................................................... 26 Register PCK at address 15H .
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FS98O22 1. Device Overview The FS98O22 is a CMOS 8-bit single chip microcontroller(MCU) with embedded a 4kx16 bits one-time programmable (OTP) ROM, a 8-channel 14-bit fully differential input analog to digital converter, low noise amplifier, and 4 x 20 LCD driver. The FS98O22 is best suited for applications such as electrical scale, meter, and sensor or transducer measurement application etc. 1.1. 8-bit single chip microcontroller(MCU).
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FS98O22 1.6. z z z 1.7. Applications Sensor or transducer measurement applications. Electronic kitchen scale, personal scale. Digital meter. Ordering Information Table 1-1 Ordering Information Description Package Type MCU with OTP ROM; The customer has to 73-pin Dice form, 100-pin LQFP program the compiled hex code into OTP ROM. MCU with program type; FSC programs the 73-pin Dice form, 100-pin LQFP customer’s compiled hex code into OTP ROM at factory before shipping.
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FS98O22 Pin Configuration FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y 1.8. Figure 1-1 FS98O22 pin configuration Rev. 1.
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FS98O22 1.9.
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FS98O22 FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y 1.10. Functional Block Diagram Figure 1-2 FS98O22 function block Rev. 1.
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FS98O22 There are 5 kinds of functional blocks in the Function Block Diagram, described as table 1-3: Table 1-3 FS98O22 main function description table Item CPU Kernel Sub Item FS98O22 CPU Core OTP Program Memory Data Memory FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y Clock sys Description Please refer to Chapter 1.11 for detailed description OTP: One Time Programmable 8k bytes is used for 4k line programming instructions FS98O22 has 256 bytes SRAM embedded in it.
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FS98O22 FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y 1.11. CPU Core Figure 1-3 FS98O22 CPU core function block The “CPU Core Block Diagram” shown in Section 1.11 mainly includes 7 important registers and 2 memory units. Please see the Figure 1-3 and the Table 1-4 for detailed information. Rev. 1.
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FS98O22 Table 1-4 FS98O22 CPU core block diagram description table Sub Items Program Counter Description This Register plays an important role in all the CPU working cycle. It records the pointer of the instruction that the CPU processes every cycle in the Program Memory. In a general CPU cycle, Program Counter pushes the Program Memory Address (12bits), instruction pointer, into the Program Memory and then increments for the next cycle.
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FS98O22 1.12. Clocking Scheme/Instruction Cycle FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y One Instruction cycle (CPU cycle) includes 4 steps and the CPU could process 2 steps per CPU Clock. Users can setup the MCK Register to decide the step timing. Please refer to Chapter 5 for related information.
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FS98O22 2. Electrical Characteristics 2.1. Absolute Maximum Ratings Table 2-1 FS98O22 absolute maximum rating table Unit V V °C °C FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y Parameter Rating Supply Voltage on VDD 3.6 Input Voltage on any pin -0.3 to VDD+0.3 Ambient Operating Temperature -40* to +85 Storage Temperature -55 to +150 Soldering Temperature, Time 260°C, 10 Sec * FS98O22 passed -40°C LTOL (Low Temperature Operating Life) test (VDD=3V) 2.2.
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FS98O22 2.3. ADC Characteristics (VDD=3V, TA=25℃, unless otherwise noted) Table 2-3 FS98O22 ADC characteristics Symbol Parameter ADC Common Mode Input Range VADIN ADC Differential Mode Input Range Resolution ADC Linearity Error ADC Input Offset Voltage With Zero Cancellation VRFIN=0.44V VRFIN=0.44V VAIN=0 -0.1 Typ. Max. Unit 0 2.3 V ±15625 0 0.6 ±31250 1 +0.1 V Counts mV 0 V FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y VACIN Test Conditions Min. INH,INL,VRH,VRL to 0.
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FS98O22 3. 3.1. Memory Organization Program Memory Structure FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y FS98O22 has an 12bits Program Counter which is capable of addressing a 4k x 16bits program memory space and a 8 level depth 12bits Stack Register. The Start up/Reset Vector is at 0x0000H. When FS98O22 is started or its program is reset, the Program Counter will point to Reset Vector. The Interrupt Vector is at 0x0004H.
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FS98O22 3.3. System Special Registers The System Special Registers are designed to complete CPU Core functions, and consists of indirect address, indirect address pointer, status register, work register, interrupt flag, and interrupt control register. Please see Section 1.11 for related CPU work flow chart. Table 3-2 system register table Address Name IND0 IND1 FSR0 FSR1 STATUS WORK INTF 07H INTE 16H 17H INTF2 INTE2 3.427 3.4.1 1.11/3.4.1 1.11/3.4.1 1.11/3.4.2 1.
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FS98O22 3.3.2. IND and FSR Registers FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y The IND (Indirect Addressing) register is not a physical register, but indirect addressing needs the IND register. Any instruction using the IND register actually accesses the register pointed by the FSR (File Select Register). While user reads data from the IND register, the CPU gets the data from the Data Memory at the address stored in FSR.
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FS98O22 3.3.3. STATUS Register The STATUS register contains the arithmetic status of ALU and the RESET status. The STATUS register is similar to other registers, and can be the destination for any instruction. If the STATUS register is the destination for an instruction that affects the Z, DC or C bit, then the writing to these three bits is disabled. These bits are set or cleared according to the device logic. The TO and PD bits are not writable.
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FS98O22 3.3.4. INTE and INTF registers The INTE and INTF registers are readable and writable registers, and contain enable and flag bits for interrupt devices.
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FS98O22 Register INTF at address 06H property U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 TMIF I2CIF ADIF E1IF E0IF INTF Bit7 TMIF: 8-bit Timer Interrupt Flag FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y Bit 4 Bit0 1 = Timer interrupt occurred (must be cleared in software) 0 = No Timer interrupt Bit 3 I2CIF: I2C Interface Interrupt Flag 1 = I2C Interface interrupt occurred (must be cleared in software) 0 = No I2C Interface interrupt Bit 2 ADIF: Analog to digital converter In
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FS98O22 3.4. Peripheral Special Registers The Peripheral Special Registers are designed for Peripheral functions, such as I/O ports, timer, ADC, signal conditional network control register, LCD driver. Please see Table 3-4 and the following Chapters for detailed description of these peripheral functions.
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FS98O22 Address Name Referenced Section 49H 54H LCD10 LCDENR 13 57H 58H 59H 5AH I2CCON I2CSTA I2CADD I2CBUF 13 Bit 6 Bit 5 Bit 4 SEG20 [3:0] LCDCKS [1:0] WCOL I2COV LCDEN I2CEN CKP DA P I2CADD [7:0] I2CBUF [7:0] Value on Bit 2 Bit 1 Bit 0 Power on Reset SEG19 [3:0] uuuuuuuu LCD_DUTY[ ENP 00000000 LEVEL 1:0] MPL 0001uuuu S RW BF uu0000u0 00000000 00000000 Bit 3 FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y 9 9 9 9 Bit 7 Rev. 1.
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FS98O22 4. Power System FS98O22 has a special power system that can supply a fixed voltage (3.6V) for CPU and ADC. FS98O22 could work when the supply voltage is within a specified range, fixed or floating. The power system has 6 function engines as Voltage Doubler, Voltage Regulator, Analog Bias Circuit, Common Voltage Generator Low Battery Comparator and Band gap Voltage / Temperature Sensor. Through the first 4 function engines, the system can generate 3 Voltage level as VGG = 2VDDP, VDDA = 3.
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FS98O22 Table 4-1 FS98O22 power system register table Address Name 15H 1CH 1DH 1FH PCK NETE NETF SVD Referenced Section 4/5/7.5/10 4/10/11 4/10/11 4.
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FS98O22 Register NETE at address 1CH property U-0 U-0 U-0 NETE R/W-0 R/W-0 ENVS R/W-0 SILB[1:0] R/W-0 ENLB Bit7 Bit0 ENVS: VDDA Voltage Source enable flag (Please read Section 4.2 for detailed description) FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y Bit 4 U-0 1 = VDDA is connected to VS. VS could be used as a voltage source. 0 = VDDA and VS are disconnected. Bit 3-2 SILB[1:0]: Low Battery Comparator Input Selector (Please refer to Section 4.
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FS98O22 Register NETF at address 1DH property U-0 NETF R/W-0 R/W-0 ENBAND ENVDDA U-0 U-0 U-0 R/W-0 R/W-0 ENAGND ENVB Bit7 ENBAND: Band gap Voltage enable flag (Please refer to Section 4.6 for detailed description) FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y Bit 6 Bit0 1 = The Band gap Voltage and Temperature Sensor are enabled, REFO to AGND is about 1.
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FS98O22 4.1. Voltage Doubler FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y C1 10uF Figure 4-2 Voltage Doubler Voltage Doubler is used for generating VGG which provide input 4 for VDDA Voltage Regulator. The inputs of Voltage Doubler are VDDP, VSSP, CA and CB. The related registers are S_PCK and ENPUMP. The Output is VGG. Please see Figure 4-2. Table 4-2 Voltage Doubler register table Address Name 14H 15H MCK PCK Referenced Section 5 4/5/7.
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FS98O22 Table 4-3 Voltage Doubler operation frequency selection table M0_CK S_PCK Voltage Doubler Operation Frequency 0 0 MCK/200 0 1 MCK/100 1 X ECK/32 FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y If the user doesn’t want the VGG to be generated from the Voltage Doubler, then the ENPUMP should be set to disable the voltage Doubler, and input the VGG pin a voltage as voltage regulator power supply. Rev. 1.
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FS98O22 Voltage Regulator FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y 4.2. Figure 4-3 Voltage regulator Voltage Regulator is used for generating VDDA (3.6V). The input is VGG which is generated by Voltage Doubler (please see the Section 4.1). The control Register flags are ENVDDA and ENVS. The Outputs are VDDA and VS. Please see Figure 4-3.
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FS98O22 Analog Bias Circuit FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y 4.3. Figure 4-4 analog bias circuit Analog Bias Circuit is used to activate VB (reference VDDA) as the power supply voltage for analog circuit (include ADC, OPAMP, Low Battery Comparator) and LCD driver. The Control register flag is ENVB. Please see Figure 4-4.
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FS98O22 Analog Common Voltage Generator FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y 4.4. Figure 4-5 analog common voltage generator Analog Common Voltage Generator is used to provide a voltage at the halt of AGND as 1/2 VDDA 6. The Control register is ENAGND and the output is AGND. Please see Figure 4-5.
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FS98O22 Low Battery Comparator FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y 4.5. Figure 4-6 low battery comparator function block Low Battery Comparator is used for VDD low voltage detection. FS98O22 embeds a voltage divider which can generate 1/2 VDD and the 1/3 VDD. A multiplexer is used to connect the voltage divides to component input. The multiplexer’s output is compares with 1.2V. The Control register flags are SILB[1:0] and the ENLB. The Output flag is LBOUT which is for read only.
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FS98O22 Bandgap Voltage and Temperature Sensor FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y 4.6. Figure 4-7 Bandgap voltage and temperature sensor function block REFO is low temperature coefficient bandgap voltage reference output. Its voltage to AGND is 1.16V, and the typical temperature coefficient is 150ppm/°C. FS98O22 embeds a Temperature Sensor to measure the IC temperature from the differential voltage between TEMPH and TEMPL (typically 550μV±50μV/°C). Its working range is 100 ~ 200 mV.
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FS98O22 5. Clock System Table 5-1 FS98O22 clock system register table Address Name MCK PCK 5 4/5/7.
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FS98O22 Oscillator State FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y 5.1. Figure 5-2 FS98O22 oscillator state block Table 5-2 FS98O22 clock system register table Address Name 14H MCK Referenced Value on Power Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Section on Reset 5 M7_CK M6_CK M5_CK M3_CK M2_CK M1_CK M0_CK 00000000 There are two clock sources in FS98O22.
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FS98O22 To enable the internal and external oscillators, users need to set the right values for M7_CK and M6_CK as shown in Table 5-4. If users execute the sleep instruction to make FS98O22 enter the SLEEP mode, both the internal oscillators and the external oscillator will be disabled. Table 5-5 oscillator state selection table Input Sleep instruction Oscillator State M7_CK X Internal External X Disable Disable FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y 1 M6_CK 7 5.2.
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FS98O22 5.3. ADC Sample Frequency FS98O22 embeds one sigma delta ADC which needs clock input to generate digital output. When users want ADC have N bits resolution digital output, ADC needs 2N clocks cycles input. (Please refer to Chapter 10 and Chapter 11 for detailed description) User should setup the M1_CK to decide the ADC sample frequency. Please see Table 5-9.
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FS98O22 5.4. Beeper Clock Table 5-10 beeper clock register table Name 14H 15H MCK PCK Referenced Bit 7 Bit 6 Bit 5 Section 5 M7_CK M6_CK M5_CK ENPU 4/5/7.5/10 MP Bit 4 Value on Power on Reset M3_CK M2_CK M1_CK M0_CK 00000000 S_BEE 00000000 S_CH1CK [1:0] S_PCK P Bit 3 Bit 2 Bit 1 Bit 0 FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y Address FS98O22 has a Beeper Clock which is used as the buzzer source. (Please refer to Section 7.
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FS98O22 Table 5-14 shows the relation between clock signals and the register flags.
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FS98O22 5.6. Chopper Operation Amplifier Input Control Signal The OPAMP embedded in FS98O22 has a chopper function to cancel the inverting and non-inverting sides voltage bias offsets. After the Chopper operation, OPAMP input voltage bias is removed. Users could setup the S_CH1CK[1:0] to choose the Chopper Control Signal.
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FS98O22 5.7. TMCLK – Timer and LCD Module Input Clock TMCLK is the clock for FS98O22 Timer and LCD Module. Users can use Table 5-20 to choose TMCLK frequency by setting the right values for M5_CK. Table 5-20 TMCLK selection table TMCLK (Timer and LCD Module input Clock) 0 CLK/1000 1 ECK/32 FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y M5_CK Rev. 1.
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FS98O22 6. Timer Module, Watch Dog Timer and Programmable Counter Table 6-1 Timer module and watch dog timer register table Address Value on Power on Reset 00u00uuu 00000000 00000000 uuuuuuuu uuuuuuuu uuuuuuuu uuuuuuuu 0000000u 0uuuu000 FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y 04H 06H 07H 08H 09H 0AH 0BH 0CH 0DH Referenced Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Section STATUS 1.11/3.4.2 -TO ---INTF 3/6/7/9/10/11 TMIF ----INTE 3/6/7/9/10/11 GIE TMIE ----CTAH 6.3 CTA[15:8] CTAL 6.
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FS98O22 Register CTBH at address 0AH property R/W-X R/W-X R/W-X CTBH R/W-X R/W-X R/W-X R/W-X R/W-X CTB[15:8] Bit7 Bit0 FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y Register CTBL at address 0BH property R/W-X R/W-X R/W-X R/W-X R/W-X R/W-X R/W-X CTB[7:0] CTBL Bit7 Bit 15-0 R/W-X Bit0 CTB[15:0]: Programmable Counter 16-bit Counter B register (Please refer to Section 6.
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FS98O22 Register CTCON at address 0CH property R/W-0 CTCON TON R/W-0 R/W-0 R/W-0 MUXSEL[2:0] R/W-0 R/W-0 R/W-0 R/W-X TE FQTMB OVAB -- Bit7 Bit 7 Bit0 TON: 16-bit Counter input signal switch (Please refer to Section 6.2 for detail) FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y 1 = The 16-bit Counter input signal switch is ON. 0 = The 16-bit Counter input signal switch is OFF. Bit 6 MUXSEL[2]: Programmable Counter Counter/Pulse Width measurement mode selector.
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FS98O22 Register WDTCON at address 0DH property R/W-0 WDTCON U-X U-X U-X U-X R/W-0 WDTEN R/W-0 WTS [2:0] Bit7 Bit0 WDTEN: Watch Dog Timer enable flag (Please refer to Section 6.2 for detail) FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y Bit 7 R/W-0 1 = Watch Dog Timer is enabled. 0 = Watch Dog Timer is disabled Bit 2-0 WTS [2:0]: Watch Dog Timer counter 2 Input Selector (Please refer to Chapter 6.
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FS98O22 Register TMOUT at address 0EH property R-0 R-0 R-0 R-0 TMOUT R-0 R-0 R-0 TMOUT [7:0] Bit7 Bit0 TMOUT [7:0]: Timer module 8-bit counter output (Please refer to Section 6.1 for detail) FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y Bit 7-0 R-0 Register TMCON at address 0FH property R/W-1 TMCON TRST U-X U-X U-X R/W-0 R/W-0 TMEN R/W-0 INS [2:0] Bit7 Bit 7 R/W-0 Bit0 TRST: Timer Module reset flag (Please refer to Section 6.
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FS98O22 6.1. Timer Module The Timer module has the following features: 8-bit Timer Counter Internal (1 MHZ) or External (32768HZ) clock selection Time out Interrupt Signal selection FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y z z z TMOUT[7:0] TMEN Out EN 8 to 1 Mux Timer Interrupt Signal 8 bits Counter TMCLK Frequency Divider TMCLK/4 CK Reset TMRST Figure 6-1 FS98O22 timer module function block Please see Figure 6-1. The input of Timer Module is TMCLK.
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FS98O22 6.1.1. Timer module interrupt Table 6-2 timer module interrupt register table Address 06H 07H Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TMIF -- -- -- -- TMIE -- -- -- -- TMOUT [7:0] TMEN Value on Power on Reset 00000000 00000000 00000000 1uuu0000 FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y 0EH 0FH Referenced Bit 7 Section INTF 3/6/7/9/10/1 1 INTE 3/6/7/9/10/1 GIE 1 TMOUT 6.1 TMCON 6.1 TRST Name INS [2:0] Operation: 1. 2. 3. 4. 5. 6. Operate as Section 5.
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FS98O22 6.1.2. Using Timer with External/Internal Clock The user could see the Table 6-4, 6-5, 6-6 and 6-7 to setup related registers to decide the clock source.
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FS98O22 Users can use Table 6-8 to select TMCLK clock source based on M0_CK, M1_CK, M3_CK and M5_CK register flag.
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FS98O22 6.2. Watch Dog Timer Watch Dog Timer Oscillator WDTA[7:0] 8 bits Counter1 Multiplex 8 bits Counter2 WDTOUT FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y WDTEN WDTS[2:0] CLRWDT Figure 6-2 watch dog timer function block Please see Figure 6-2. WDT (Watch Dog Timer) is used to prevent the program from being out of control by any uncertain reason. When WDT is active, it will reset the CPU when the WDT timeout.
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FS98O22 6.3.
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FS98O22 z Counter mode: There are two 16-bit counters (CTA and CTB) in Programmable Counter unit. Operation: 1. 2. Clear FQTMB and MUXSEL[2] register flags to make the Programmable Counter work as Counter. Setup MUXSEL[1:0] to decide the input clock signal. Table 6-11 Programmable Counter Clock signal selection table Clock signal PFI ECK Instruction Cycle ICK FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y MUXSEL[1:0] 11 10 01 00 3. 4. 5. 6. 7. 8. 9.
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FS98O22 z Pulse Width Measurement mode: Programmable Counter could be used to measure the time when a signal holds its voltage level in high or low. Operation: 1. 2. 3. FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y 4. Clear FQTMB and clear MUXSEL[2] register flags to make the Programmable Counter work as Pulse Width Measurement. Setup MUXSEL[1:0] to decide the input clock signal. PFI is the signal which is ready to measure the pulse width. Users could set TE to invert the PFI voltage level.
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FS98O22 z Frequency Measurement mode: Programmable Counter could be used to measure a signal frequency. Operation: 1. 2. 3. 4. FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y 5. 6. Set FQTMB and clear MUXSEL[2] register flags to make the Programmable Counter work as Frequency Measurement. Setup MUXSEL[1:0] to decide the input clock signal. PFI is the signal which is ready to measure the frequency. Users could set TE to invert the PFI voltage level.
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FS98O22 7.
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FS98O22 Register PT1 at address 20H property R/W-X R/W-X R/W-X PT1 R/W-X R/W-X R/W-X R/W-X R/W-X PT1 [7:0] Bit7 Bit 7-0 Bit0 PT1[7:0]: GPIO Port 1 data flag (Please refer to Section 7.
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FS98O22 property R/W-0 R/W-0 R/W-0 PT1PU R/W-0 R/W-0 R/W-0 R/W-0 PT1PU [7:0] Bit7 Bit 7-0 R/W-0 Bit0 PT1PU [7:0]: GPIO Port 1 Pull up resistor enable flag (Please refer to Section 7.
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FS98O22 Register AIENB1 at address 23H property R/W-0 R/W-0 R/W-0 AIENB1 R/W-0 R/W-0 R/W-0 R/W-0 AIENB[7:0] Bit7 Bit 7-0 R/W-0 Bit0 AIENB1[7:0]: GPIO Port 1 Analog / Digital control flag (Please refer to Section 7.
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FS98O22 Register PT2 at address 24H property R/W-X R/W-X R/W-X PT2 R/W-X R/W-X R/W-X R/W-X PT2 [7:0] Bit7 Bit 7-0 R/W-X Bit0 PT2[7 :0] : GPIO Port 2 data flag FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y PT2[7] = GPIO Port 2 bit 7 data flag PT2[6] = GPIO Port 2 bit 6 data flag PT2[5] = GPIO Port 2 bit 5 data flag PT2[4] = GPIO Port 2 bit 4 data flag PT2[3] = GPIO Port 2 bit 3 data flag PT2[2] = GPIO Port 2 bit 2 data flag PT2[1] = GPIO Port 2 bit 1 data flag PT2[0] = GPIO Port 2 bit
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FS98O22 Register PT2EN at address 25H property R/W-0 R/W-0 R/W-0 PT2EN R/W-0 R/W-0 R/W-0 R/W-0 PT2EN [7:0] Bit7 Bit 7-0 R/W-0 Bit0 PT2EN [7 :0] : GPIO Port 2 Input / Output control flag FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y PT2EN[7] = GPIO Port 2 bit 7 I/O control flag ; 0 = defined as input port, 1 = defined as output port PT2EN[6] = GPIO Port 2 bit 6 I/O control flag ; 0 = defined as input port, 1 = defined as output port PT2EN[5] = GPIO Port 2 bit 5 I/O control flag ; 0 =
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FS98O22 Register PT2PU at address 26H R/W-0 R/W-0 R/W-0 PT2PU R/W-0 R/W-0 R/W-0 R/W-0 PT2PU [7:0] Bit7 Bit 7-0 R/W-0 Bit0 PT2PU [7:0]: GPIO Port 2 Pull up resistor enable flag FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y PT2PU[7] = GPIO Port 2 bit 7 control flag ; 0 = Pull up resistor is disconnect, 1 = with Pull up resistor PT2PU[6] = GPIO Port 2 bit 6 control flag ; 0 = Pull up resistor is disconnect, 1 = with Pull up resistor PT2PU[5] = GPIO Port 2 bit 5 control flag ; 0 = Pul
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FS98O22 Register PT2MR at address 27H property R/W-0 PT2MR BZEN U-0 U-0 R/W-0 PM1EN R/W-0 R/W-0 E1M[1:0] R/W-0 E0M[1:0] Bit7 Bit 7 R/W-0 Bit0 BZEN: Buzzer enable flag (Please refer to Section 7.5 for detail) FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y 1 = Buzzer function is enabled, GPIO Port 2 bit 7 is defined as Buzzer output. 0 = Buzzer function is disabled, GPIO Port 2 bit 7 is defined as GPIO.
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FS98O22 Register PT3 at address 28H property R/W-X R/W-X R/W-X PT3 R/W-X R/W-X R/W-X R/W-X PT3 [7:0] Bit7 Bit0 PT3[7 :0] : GPIO Port 3 data flag FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y Bit 7-0 R/W-X PT3[7] = GPIO Port 3 bit 7 data flag PT3[6] = GPIO Port 3 bit 6 data flag PT3[5] = GPIO Port 3 bit 5 data flag PT3[4] = GPIO Port 3 bit 4 data flag PT3[3] = GPIO Port 3 bit 3 data flag PT3[2] = GPIO Port 3 bit 2 data flag PT3[1] = GPIO Port 3 bit 1 data flag PT3[0] = GPIO Port 3 bit
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FS98O22 Register PT3EN at address 29H property R/W-0 R/W-0 R/W-0 PT3EN R/W-0 R/W-0 R/W-0 R/W-0 PT3EN [7:0] Bit7 Bit 7-0 R/W-0 Bit0 PT3EN [7 :0] : GPIO Port 3 Input / Output control flag FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y PT3EN[7] = GPIO Port 3 bit 7 I/O control flag ; 0 = defined as input port, 1 = defined as output port PT3EN[6] = GPIO Port 3 bit 6 I/O control flag ; 0 = defined as input port, 1 = defined as output port PT3EN[5] = GPIO Port 3 bit 5 I/O control flag ; 0 =
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FS98O22 Register PT3PU at address 2AH R/W-0 R/W-0 R/W-0 PT3PU R/W-0 R/W-0 R/W-0 R/W-0 PT3PU [7:0] Bit7 Bit 7-0 R/W-0 Bit0 PT3PU [7:0]: GPIO Port 3 Pull up resistor enable flag FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y PT3PU[7] = GPIO Port 3 bit 7 control flag ; 0 = Pull up resistor is disconnected, 1 = with Pull up resistor PT3PU[6] = GPIO Port 3 bit 6 control flag ; 0 = Pull up resistor is disconnected, 1 = with Pull up resistor PT3PU[5] = GPIO Port 3 bit 5 control flag ; 0 =
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FS98O22 Register PT3MR at address 2BH property R/W-0 U-0 U-0 PT3MR R/W-0 R/W-0 PFOEN R/W-0 E3M[1:0] R/W-0 E2M[1:0] Bit7 Bit 4 R/W-0 Bit0 PFOEN: Programmable Counter Enabled register flag FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y 1 = Programmable Counter is enabled 0 = Programmable Counter is disabled Bit 3-2 E3M[1:0]: GPIO Port 3 bit 1 interrupt trigger mode (Please refer to Section 7.
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FS98O22 Register PT2OCB at address 37H property U-X U-X U-X PT2OCB R/W-1 R/W-1 U-X U-X PT2OC[4:3] Bit7 Bit 4-3 U-X Bit0 PT2OC[4:3]: GPIO Port 2 Open Drain control flag FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y PT2OC[4] = GPIO Port 2 bit 4 Open Drain control flag ; 0 = normal digital I/O, 1 = Open Drain Control PT2OC[3] = GPIO Port 2 bit 3 Open Drain control flag ; 0 = normal digital I/O, 1 = Open Drain Control property R = Readable bit W = Writable bit U = unimplemented bi
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FS98O22 Digital I/O Port with Analog Input Channel Shared: PT1[7:0] FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y 7.1. Figure 7-1 PT1[7:0] function block GPIO Port 1 (PT1[7:0]) function block is shown in Figure 7-1. The main function of the GPIO is for data exchange between the Data bus and the ports. Users could control the PT1EN[7:0] register flags to decide the input and output direction.
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FS98O22 Table 7-2 PT1 register table Address Name 20H 21H 22H 23H PT1 PT1EN PT1PU AIENB1 Detail on Chapter 7 7 7 7 Bit 7 Bit 6 AIENB[7:6] Bit 5 Bit 4 Bit 3 Bit 2 PT1 [7:0] PT1EN [7:0] PT1PU [7:0] AIENB[5:0] Bit 1 Bit 0 Value on Power on Reset uuuuuuuu 00000000 00000000 00000000 Read data Operation 10 Clear the PT1EN[n] register flags. The PT1[n] will be defined as an input port. Set the PT1PU[n] register as required. The PT1[n] will be connected to an internal pull up resistor.
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FS98O22 Digital I/O Port and External Interrupt Input : PT2[0], PT2[1], PT3[0], PT3[1] FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y 7.2. Figure 7-2 PT2[0] PT2[1] PT3[0] PT3[1] function block GPIO Port 2 Bit1 and Bit 0 (PT2[1:0])and Port 3 Bit1 and Bit 0 (PT3[1:0]) function block is shown in Figure 7-2. The main function of the GPIO is input and output data between the Data bus and the ports. Users could control the PT2EN[1:0] and PT3EN[1:0] register flags to decide the input output direction.
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FS98O22 Table 7-3 PT2 register table 06H 07H 24H 25H 26H 27H 28H 29H 2AH Referenced Bit 7 Section INTF 3/6/7/9/10/11 INTE 3/6/7/9/10/11 GIE PT2 7 PT2EN 7 PT2PU 7 PT2MR 7.2/7.
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FS98O22 Digital I/O Port or PDM Output : PT2[2] and PT2[5] FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y 7.3. Figure 7-3 PT2[2] function block GPIO Port 2 Bit2 (PT2[2]) and GPIO Port 2 Bit5 (PT2[5]) function block is shown in Figure 7-3. The main function of the GPIO is input and output data between the Data bus and the ports. User could control the PT2EN[2]/ PT2EN[5] register flags to decide the input output direction.
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FS98O22 Table 7-4 PT2 register table Address Name 24H 25H 26H 27H PT2 PT2EN PT2PU PT2MR Detail on Chapter 7 7 7 7.2/7.5/8 Bit 7 -- Bit 6 Bit 5 PM2EN Bit 4 Bit 3 Bit 2 Bit 1 PT2 [7:0] PT2EN [7:0] PT2PU [7:0] PM1EN -- Bit 0 -- Value on Power on Reset uuuuuuuu 00000000 00000000 00000000 Read data Operation 15 Clear the PT2EN[n] register flags. The PT2[n] will be defined as an input port. Set the PT2PU[n] register as required. The PT2[n] will be connected to an internal pull up resistor.
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FS98O22 z Input: GPIO Port 2 Bit4 and Bit3 (PT2[4:3]) could be the I2C Module SCL and SDA ports or be the general I/O ports. User should setup I2CEN register flag to decide the I2C Module is enabled or not. The detailed I2C Module usage is described in Chapter 9. The input port has a Schmitt trigger in it, and the up/down trigger voltage level is 0.45VDD/0.2VDD. z Output FS98O22 sends the digital data out by an embedded D Flip Flop.
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FS98O22 Digital I/O Port : PT2[6] FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y 7.5. Figure 7-5 PT2[6] function block GPIO Port 2 Bit 6 (PT2[6]) function block is shown in Figure 7-5. The main function of the GPIO is input and output data between the Data bus and the ports. Users could control the PT2EN[6] register flags to decide the input output direction. The input and output function are explained as follows: z Input: GPIO Port 2 Bit 6 (PT2[6]) could only be the general I/O ports.
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FS98O22 Table 7-6 PT2 register table Address 24H 25H 26H 27H Referenced Bit 7 Section PT2 7 PT2EN 7 PT2PU 7 PT2MR 7.2/7.5/8 BZEN Name Bit 6 Bit 5 Bit 4 Bit 3 PT2 [7:0] PT2EN [7:0] PT2PU [7:0] --- Bit 2 Bit 1 Bit 0 -- Value on Power on Reset uuuuuuuu 00000000 00000000 00000000 Read data Operation 19 Clear the PT2EN[n] register flags. The PT2[n] will be defined as an input port. Set the PT2PU[n] register as required. The PT2[n] will be connected to an internal pull up resistor.
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FS98O22 Digital I/O Port or Buzzer Output : PT2[7] FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y 7.6. Figure 7-6 PT2[7] function block GPIO Port 2 Bit2 (PT2[2]) function block is shown in Figure 7-6. The main function of the GPIO is input and output data between the Data bus and the ports. Users could control the PT2EN[2] register flags to decide the input output direction.
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FS98O22 Table 7-7 PT2[7] register table Address Name 24H 25H 26H PT2 PT2EN PT2PU Referenced Section 7 7 7 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PT2 [7:0] PT2EN [7:0] PT2PU [7:0] Value on Power on Reset uuuuuuuu 00000000 00000000 Read data Operation 21 Clear the PT2EN[n] register flags. The PT2[n] will be defined as an input port. Set the PT2PU[n] register as required. The PT2[n] will be connected to an internal pull up resistor.
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FS98O22 8. PDM (Pulse Density Modulator) Module FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y Please see Figure 8-1 and Figure 8-2. The GPIO port 2 bit 2 (PT2[2]) could be defined as either PDM module output or General purpose I/O. User could control the PDMEN register flags to decide the definition. The PDM module is the function FS98O22 uses for implementing the PWM (Pulse Width Modulation). Its working flowchart and usage will be described in this Chapter.
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FS98O22 PDM15 PDM14 PDM13 PDM12 … … FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y If PMD1 = 0x5000H PDM out If PMD1 = 0xC000H PDM out Figure 8-2 PDM module signal generation Rev. 1.
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FS98O22 Table 8-1 PDM module register table Address Name 27H 30H 31H 32H 33H 36H PT2MR PMD1H PMD1L PMD2H PMD2L PMCON Referenced Section 7.2/7.
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FS98O22 Register PMD1H at address 30H property R/W-0 R/W-0 R/W-0 PMD1H R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PMD1[15:8] Bit7 Bit0 Register PMD1L at address 31H R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y property PMD1[7:0] PMD1L Bit7 Bit 15-0 Bit0 PMD1[15:0]: PDM Module Data output Control Register PMD1[15] = PDM15 (PDM CLK/21)Signal Combination enable flag.
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FS98O22 Register PMD2H at address 30H property R/W-0 R/W-0 R/W-0 PMD2H R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PMD2[15:8] Bit7 Bit0 FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y Register PMD2L at address 31H property R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PMD2[7:0] PMD2L Bit7 Bit 15-0 Bit0 PMD2[15:0]: PDM Module Data output Control Register PMD2[15] = PDM15 (PDM CLK/21)Signal Combination enable flag.
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FS98O22 Register PMCON at address 36H property U-0 U-0 U-0 PMCON R/W-0 U-0 R/W-0 PDMEN R/W-0 PMCS[2:0] Bit7 Bit 4 R/W-0 Bit0 PDMEN: PDM Module enable flag (Please refer to Chapter 8 for details) FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y 1 = PDM Module is enabled, GPIO Port 2 bit 2 could be defined as PDM output. 0 = PDM Module is disabled, GPIO Port 2 bit 2 could be defined as GPIO.
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FS98O22 Table 8-2 PMD register table Address 14H 25H 27H Value on Power on Reset 00000000 00000000 00000000 00000000 00000000 00000000 FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y 30H 31H 36H Detail on Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Chapter MCK 5 M7_CK M6_CK M5_CK M3_CK M2_CK M1_CK M0_CK PT2EN 7 PT2EN [7:0] PT2MR PM1E 7.2/7.5/8 ---N PMD1H 8 PMD1[15:8] PMD1L 8 PMD1[7:0] PMCON PDME 8 PMCS[2:0] N Name PDM Operation 1. 2. 3. 4. 5. 6. Setup M0_CK, M3_CK to decide the MCK.
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FS98O22 9. I2C Module (slave mode only) FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y FS98O22 embeds a slave mode I2C module. The two pins, SCL and SDA, are used to perform the I2C system. The pin SCL is assigned to be the clock pin, and the pin SDA is assigned to be the data pin in the I2C module. In an I2C system, there are master side and slave side. Master side would send the clock, slave ID and the commands to slave side. One master could connect to several slave sides with different IDs.
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FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y FS98O22 Figure 9-2 I2C module function block Rev. 1.
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FS98O22 Table 9-1 I2C module register table Address Name 57H 58H 59H 5AH I2CCON I2CSTA I2CADD I2CBUF Referenced Bit 7 Bit 6 Bit 5 Section 9 WCOL I2COV I2CEN 9 DA 9 9 Bit 4 Bit 3 CKP P S I2CADD [7:0] I2CBUF [7:0] Bit 2 Bit 1 Value on Power on Reset 0001uuuu uu0000u0 00000000 00000000 Bit 0 RW BF FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y Register I2CCON at address 57H property R/W-0 R/W-0 R/W-0 R/W-1 I2CCON WCOL I2COV I2CEN CKP U-X U-X U-X Bit7 Bit 7 U-X Bit0 WCOL:
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FS98O22 Register I2CSTA at address 58H property U-X U-X I2CSTA R/W-0 R/W-0 R/W-0 R/W-0 DA P S RW U-X BF Bit7 Bit0 DA: Data / Address bit register flag. FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y Bit 5 R/W-0 1 = The last received byte is data. 0 = The last received byte is address. Bit 4 P: Stop bit register flag 1 = A stop bit is detected. 0 = No stop bit is detected. When the I2C module is disabled, this bit would be clear.
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FS98O22 Register I2CBUF at address 5AH property R/W-0 R/W-0 R/W-0 I2CBUF R/W-0 R/W-0 R/W-0 R/W-0 I2CBUF [7:0] Bit7 Bit0 I2CBUF[7:0]: I2C module Data buffer register. FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y Bit 7-0 R/W-0 Property R = Readable bit W = Writable bit U = unimplemented bit - n = Value at Power On Reset ‘1’ = Bit is Set ‘0’ = Bit is Cleared Rev. 1.
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FS98O22 Table 9-2 I2C register table Address Referenced Section Bit 7 INTF 3/6/7/9/10/11 INTE 3/6/7/9/10/11 GIE PT2OCB 9 I2CCON 9 WCOL I2CSTA 9 I2CADD 9 I2CBUF 9 Bit 6 I2COV Bit 5 I2CEN DA Bit 4 Bit 3 -I2CIF -I2CIE PT2OC[4:3] CKP P S I2CADD [7:0] I2CBUF [7:0] Bit 2 Bit 1 Bit 0 --- --- --- RW BF Value on Power on Reset 00000000 00000000 uuu11uuu 0001uuuu uu0000u0 00000000 00000000 FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y 06H 07H 37H 57H 58H 59H 5AH Name I2C data receive o
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FS98O22 I2C data transmit operation: 1. 2. 3. 4. 5. 6. FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y 7. 8. 9. Configure SCL and SDA pins as open-drain through the PTOCB[4:3]. Set I2CEN register flag to enable the I2C module. Clear I2CIF to reset the I2C interrupt. Set I2CIE and GIE to enable the I2C interrupt. Wait for the interrupt. When the I2C master device sends data to slave side, the data (ID) transmitted from the master device will be sent to I2CBUF, and the BF register flag will be set.
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FS98O22 10. Analog Function Network Please see Figure 10-1. FS98O22 Analog Function Network has 2 main functions: Low Noise OP Amplifier (OPAMP) and Sigma Delta Analog to Digital Converter (ADC). OPAMP is used to amplify the input analog signal for ADC. ADC is used to convert the analog signal to digital signal. The OPAMP has 2 input ports as inverting side and non-inverting side. Users could setup SOP1P[2:0] and SOP1N[1:0] to choose the input signals.
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FS98O22 Table 10-1 analog function network register table Address Name INTF INTE ADOH ADOL ADOLL ADCON PCK NETA NETB NETC NETD Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 --ADIF ----ADIE --ADO [15:8] ADO [7:0] Extra ADC output register ADRST ADM [2:0] S_CH1CK [1:0] --SINH[2:0] SFTA[2:0] SOP1N[1:0] SVRL[1:0] SVRH[1:0] ADG[1:0] ADEN AZ OP1EN SOP1P[2:0] Value on Power on Reset 00000000 00000000 00000000 00000000 00000000 uuuu0000 00000000 00000000 00000000 00000000 00000000 FO Fo P R r R ro TU ef pe NE er rt
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FS98O22 Register ADOH at address 10H Property R-0 R-0 R-0 R-0 ADOH R-0 R-0 R-0 R-0 ADO [15:8] Bit0 FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y Bit7 Register ADOL at address 11H property R-0 R-0 R-0 R-0 ADOL R-0 R-0 R-0 ADO [7:0] Bit7 Bit 15-0 R-0 Bit0 ADO [15:0]: ADC Digital Output ADO[15] = ADC Digital Output sign bit. 0 = Output is positive; 1 = Output is negative. ADO[14] = ADC Digital Output sign bit. 0 = Output is positive; 1 = Output is negative.
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FS98O22 Register ADOLL at address 12H property R-0 R-0 R-0 ADOLL R-0 R-0 R-0 R-0 R-0 Extra ADC output register Bit7 Bit0 FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y Users could take the value of 3 registers, ADOH, ADOL and ADOLL as 24 bits ADC output. Register ADCON at address 13H property U-X U-X U-X U-X ADCON R/W-0 R/W-0 ADRST R/W-0 ADM [2:0] Bit7 Bit 3 R/W-0 Bit0 ADRST: ADC comb filter enable register (Please refer to Section 10.
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FS98O22 Register PCK at address 15H property U-0 PCK U-0 U-0 -- U-0 R/W-0 R/W-0 S_CH1CK [1:0] U-0 U-0 -- -- Bit7 S_CH1CK [1:0]: OPAMP Control Register (Please refer to Section 10.2) FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y Bit 3-2 Bit0 11 = The OPAMP Chopper mode is enabled, and the Chopper frequency is CLK/1000 10 = The OPAMP Chopper mode is enabled, and the Chopper frequency is CLK/500 01 = The OPAMP Chopper mode is disabled.
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FS98O22 Register NETA at address 18H property R/W-0 NETA R/W-0 R/W-0 SINL[1:0] R/W-0 R/W-0 R/W-0 SINH[2:0] R/W-0 SFTA[2:0] Bit7 Bit0 SINL[1:0]: ADC negative input port signal multiplexer (Please refer to Section 10.1) FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y Bit 7-6 R/W-0 11 = The ADC negative input port is connected to TEMPL. (Please refer to Section 4.6) 10 = The ADC negative input port is connected to AIN3 (PT1[3]).
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FS98O22 Register NETB at address 19H property U-0 U-0 NETB R/W-0 R/W-0 SOP1N[1:0] R/W-0 R/W-0 R/W-0 SVRL[1:0] SVRH[1:0] Bit7 Bit0 SOP1N[1:0]: OPAMP inverting input port signal multiplexer (Please refer to Section 10.2) FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y Bit 5-4 R/W-0 11 = The OPAMP inverting input port is connected to AIN6 (PT1[3]). 10 = The OPAMP inverting input port is connected to AIN5 (PT1[5]). 01 = The OPAMP inverting input port is connected to AIN4 (PT1[4]).
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FS98O22 Register NETC at address 1AH property R/W-0 NETC SREFO U-0 U-0 U-0 R/W-0 R/W-0 ADG[1:0] R/W-0 R/W-0 ADEN AZ Bit7 SREFO: Internal Reference Voltage enable flag. (Please refer to Section 10.1) FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y Bit 7 Bit0 1 = Internal Reference Voltage is enabled. VR1P = 2/5 REFO, VR2P = 1/5 REFO 0 = Internal Reference Voltage is disabled. VR1P and VR2P are floating. Bit 3-2 ADG[1:0]: Internal ADC input gain. (Please refer to Section 10.
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FS98O22 Register NETD at address 1BH property U-0 U-0 U-0 NETD U-0 R/W-0 R/W-0 OP1EN R/W-0 SOP1P[2:0] Bit7 Bit0 OP1EN: OPAMP enable flag. (Please refer to Section 10.2) FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y Bit 3 R/W-0 1 = OPAMP is enabled. 0 = OPAMP is disabled. Bit 2-0 10.
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FS98O22 10.1. Analog to Digital Converter (ADC) : FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y Please see Figure 10-2. ADC Module contains 3 main functions – Low Pass Filter, Sigma Delta Modulator and Comb Filter. Before doing the AD conversion, User could reduce the low frequency noise by the embedded Low Pass Filter. The SINH[2:0] register flags are used to choose the input signal. SFTA[2] flag is used to enable the Filter.
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FS98O22 Table 10-2 ADC function register table Address 06H 07H Bit 5 -- Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 -- -- ADIF -- -- -- -- ADIE -- -- ADO [15:8] ADO [7:0] ADRST ---SINH[2:0] -SVRL[1:0] ADG[1:0] ADM [2:0] M1_CK -SFTA[2:0] SVRH[1:0] ADEN AZ Value on Power on Reset 00000000 00000000 00000000 00000000 uuuu0000 00000000 00000000 00000000 00000000 FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y 10H 11H 13H 14H 18H 19H 1AH Referenced Bit 7 Bit 6 Section INTF 3/6/7/9/10/1 1 INTE 3/6/
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FS98O22 Table 10-5 INH selection table INH (ADC positive input port signal) 00 FTB 01 FTIN 10 AIN2 11 AIN3 FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y SFTA[1:0] 5. Set SINL[1:0] to decide the ADC negative input port signal. (Table 10-6) Table 10-6 INL selection table 6. SINL[1:0] INL (ADC negative input port signal) 00 AIN1 01 AIN2 10 AIN3 11 TEMPL Set ADG[1:0] to decide the ADC input gain. (Table 10-7) Table 10-7 ADG selection table 7. 8.
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FS98O22 Table 10-9 SVRL selection table VRL (ADC reference voltage negative input) 00 AGND 01 AIN1 10 AIN2 11 VR2P FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y SVRL[1:0] 10. Set ADM[2:0] to decide the ADC output rate.
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FS98O22 10.2. OPAMP : OP1 Table 10-12 FS98O22 OPAMP register table Address Name 15H 19H 1BH PCK NETB NETD Referenced Section 4/5/7.5/10 10/11 10/11 Bit 7 Bit 6 Bit 5 Bit 4 -SOP1N[1:0] Bit 3 Bit 2 Bit 1 Bit 0 S_CH1CK [1:0] ----OP1EN SOP1P[2:0] Value on Power on Reset 00000000 00000000 00000000 FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y OPAMP Operation 1. Set SOP1P[2:0] to decide the OPAMP non-inverting input port signal. (Table 10-13) Table 10-13 OP1P selection table 2.
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FS98O22 Table 10-15 chopper mode selection table OPAMP chopper mode (input operation) 00 +Offset 01 -Offset 10 CLK/500 chopper frequency 11 CLK/1000 chopper frequency FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y S_CH1CK[1:0] 4. Set OP1EN to enable the OPAMP. Rev. 1.
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FS98O22 11. ADC Application Guide The ADC used in FS98O22 is a ∑-Δ ADC with fully differential inputs and fully differential reference voltage inputs. Its maximum output is ±15625. The conversion equation is as follows: Dout = 15625 * G * G is ADC input gain. (refer to Section 10.1 ADC operation step 6) VIH is ADC’s positive input voltage VIL is ADC’s negative input voltage Vio is ADC’s offset on the input terminals (Vio could be measured by using AZ register flag. See Section 11.
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FS98O22 To get a correct ADC result, Doff(ADC input offset digital output) should be deducted from the Dout. The instruction is as follows: 1. 2. 3. 4. Set AZ bit, and VIH and VIL will short. Dout will be 15625 *G * (Vio) / (VRH-VRL+Vro). It’s called Doff. Save Doff in memory, and then Clear AZ bit to restart the ADC module. Pass the first 2 ADC interrupts for ignoring the unstable ADC result. When measuring analog signal, Doff should be deducted. 11.5.
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FS98O22 12. Low Noise Operation Amplifier Guide The input noise of CMOS OPAMP is generally much larger than the one of a Bipolar OPAMP. Moreover, the flick noise (1/f noise) of CMOS is a killer for low frequency small signal measurement. But the need for input bias current in Bipolar OPAMP causes that some transducers can not be used. In general, bipolar process is not good for highly integrated Ics.
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FS98O22 12.2. Differential Amplifier Measurement of differential signal is often used in bridge sensor applications. As shown in the differential amplifier below, VS Pin is used as power input for bridge sensor, ADC reference voltage is also from VS Pin after voltage division. When there is a small change in VS, ADC output does not change. Connecting AIN2 to ADC negative input can adjust the zero point of bridge sensor. When starting chopper mode, the amplification should be less than 100 times.
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FS98O22 13. LCD Driver FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y FS98O22 embeds a LCD driver. The control signal are COM1~COM4 and SEG1~SEG12. The user could set the SEG register flags to drive a static or multiplexed LCD panel. FS98O22 LCD driver could drive up to 20 segments multiplexed with up to 4 commons. Please see Figure 13-1.
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FS98O22 The LCD frame frequency could be setup by setting the LCDCKS[1:0] register flags. FS98O22 divides the LCD Module input clock to get LCDCK.
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FS98O22 LCDCK COM1 1/4 duty COM2 COM3 COM4 COM1 COM2 COM3 FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y 1/3 duty COM4 COM1 1/2 duty COM2 COM3 COM4 COM1 static COM2 COM3 COM4 Figure 13-3 LCD duty mode working cycle Rev. 1.
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FS98O22 FS98O22 LCD driver has 3 voltage bias ports, such as V1, V2 and V3, and 2 kinds of power mode: 1/3 bias and 1/2 bias. Please see the following description to setup the LCD power system. 1/3 bias power system (Please see Figure 13-4 and 13-5) FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y z Figure 13-4 1/3 bias LCD power system circuit connection example 1/4 duty, 1/3 bias 1/3duty, 1/3bias Figure 13-5 1/3 bias LCD power system clock Rev. 1.
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FS98O22 1/2 bias power system (Please see Figure 13-6 and 13-17) FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y z Figure 13-6 1/2 bias LCD power system circuit connection example 1/4 duty, 1/2 bias 1/3duty, 1/2bias Figure 13-7 1/2 bias LCD power system clock Rev. 1.
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FS98O22 Table 13-3 FS98O22 LCD driver register table Address Bit 4 Value on Power on Reset SEG1 [3:0] uuuuuuuu SEG3 [3:0] uuuuuuuu SEG5 [3:0] uuuuuuuu SEG7 [3:0] uuuuuuuu SEG9 [3:0] uuuuuuuu SEG11 [3:0] uuuuuuuu SEG13 [3:0] uuuuuuuu SEG15 [3:0] uuuuuuuu SEG17 [3:0] uuuuuuuu SEG19 [3:0] uuuuuuuu LEVEL LCD_DUTY[1:0] ENPMPL 00000000 Bit 3 Bit 2 Bit 1 Bit 0 FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y 40H 41H 42H 43H 44H 45H 46H 47H 48H 49H 54H Referenced Bit 7 Bit 6 Bit 5 Section LCD1 13 SEG2
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FS98O22 Register LCD2 at address 41H property R/W-X R/W-X LCD2 R/W-X R/W-X R/W-X R/W-X SEG4 [3:0] R/W-X SEG3 [3:0] Bit7 Bit0 SEG4[3]: LCD driver control signal: SEG4 with COM4 data. FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y Bit 7-4 R/W-X SEG4[2]: LCD driver control signal: SEG4 with COM3 data. SEG4[1]: LCD driver control signal: SEG4 with COM2 data. SEG4[0]: LCD driver control signal: SEG4 with COM1 data. Bit 3-0 SEG3[3]: LCD driver control signal: SEG3 with COM4 data.
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FS98O22 Register LCD4 at address 43H property R/W-X R/W-X LCD4 R/W-X R/W-X R/W-X R/W-X SEG8 [3:0] R/W-X SEG7 [3:0] Bit7 Bit0 SEG8[3]: LCD driver control signal: SEG8 with COM4 data. FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y Bit 7-4 R/W-X SEG8[2]: LCD driver control signal: SEG8 with COM3 data. SEG8[1]: LCD driver control signal: SEG8 with COM2 data. SEG8[0]: LCD driver control signal: SEG8 with COM1 data. Bit 3-0 SEG7[3]: LCD driver control signal: SEG7 with COM4 data.
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FS98O22 Register LCD6 at address 45H property R/W-X R/W-X LCD6 R/W-X R/W-X R/W-X R/W-X SEG12 [3:0] R/W-X R/W-X SEG11 [3:0] Bit0 FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y Bit7 Bit 7-4 SEG12[3]: LCD driver control signal: SEG12 with COM4 data. SEG12[2]: LCD driver control signal: SEG12 with COM3 data. SEG12[1]: LCD driver control signal: SEG12 with COM2 data. SEG12[0]: LCD driver control signal: SEG12 with COM1 data.
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FS98O22 Register LCDENR at address 54H property LCDENR R/W-0 R/W-0 LCDCKS [1:0] R/W-0 U-0 LCDEN R/W-0 LEVEL R/W-0 LCD_DUTY[1:0] Bit7 Bit 7-6 R/W-0 R/W-0 ENPMPL Bit0 LCDCKS[1:0]: LCD frame frequency selector FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y 11 = LCD frame frequency is assigned to be LCD input clock frequency/8 10 = LCD frame frequency is assigned to be LCD input clock frequency/16 01 = LCD frame frequency is assigned to be LCD input clock frequency/32 00 = LCD frame fre
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FS98O22 Table 13-4 LCD driver register table Address Name Referenced Section 14H 40H 41H 42H 43H 44H 45H 46H 47H 48H 49H 54H MCK LCD1 LCD2 LCD3 LCD4 LCD5 LCD6 LCD7 LCD8 LCD9 LCD10 LCDENR 5 13 13 13 13 13 13 13 13 13 13 13 Bit 7 Bit 6 Bit 5 Bit 4 -M5_CK SEG2 [3:0] SEG4 [3:0] SEG6 [3:0] SEG8 [3:0] SEG10 [3:0] SEG12 [3:0] SEG14 [3:0] SEG16 [3:0] SEG18 [3:0] SEG20 [3:0] LCDCKS [1:0] LCDEN Bit 2 Bit 1 M3_CK Bit 0 -M1_CK M0_CK SEG1 [3:0] SEG3 [3:0] SEG5 [3:0] SEG7 [3:0] SEG9 [3:0] SEG11 [3:0] SEG1
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FS98O22 Table 13-8 LCD frame frequency selection table LCDCKS [1:0] LCD frame frequency (LCDCK) LCD Input clock Frequency/8 01 LCD Input clock Frequency/16 10 LCD Input clock Frequency/32 11 LCD Input clock Frequency/64 FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y 00 6. Setup LCD_DUTY[1:0] register flag to decide the control mode.(SEG duty cycle) Table 13-9 LCD duty control mode selection table 7.
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FS98O22 14. Halt and Sleep Modes FS98O22 supports low power working mode. When the user want FS98O22 to do nothing and just stand by, FS98O22 could be set to Halt mode or Sleep mode to reduce the power consumption by stopping the CPU core working. The two modes will be described below. z Halt Mode FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y After CPU executes a Halt command, CPU Program Counter (PC) stops counting until an interrupt command is issued.
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FS98O22 Instruction Set The FS98O22 instruction set consists of 37 instructions. Each instruction could be converted to 16-bit OPCODE. The detailed descriptions are shown in the following sections. 14.1.
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FS98O22 Note: f: memory address (00h ~ 7Fh). W: work register. k: literal field, constant data or label. d: destination select: d=0 store result in W, d=1: store result in memory address f. b: bit select (0~7). [f]: the content of memory address f. PC: program counter. C: Carry flag DC: Digit carry flag Z: Zero flag PD: power down flag TO: watchdog time out flag WDT: watchdog timer counter FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y Rev. 1.
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FS98O22 14.2.
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FS98O22 Add W, f and Carry ADDWFC f, d 0 ≤ f ≤ FFh d ∈ [0,1] Operation [Destination] ← [f] + [W] + C Flag Affected C, DC, Z Description Add the content of the W register, [f] and Carry bit. If d is 0, the result is stored in the W register. If d is 1, the result is stored back in f.
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FS98O22 BCF Syntax FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y Operation Flag Affected Description Cycle Example: BCF FLAG, 2 Bit Clear f BCF f, b 0 ≤ f ≤ FFh 0≤b≤7 [f] ← 0 None Bit b in [f] is reset to 0. 1 Before instruction: FLAG = 8Dh After instruction: FLAG = 89h BSF Syntax Operation Flag Affected Description Cycle Example: BSF FLAG, 2 Bit Set f BSF f, b 0 ≤ f ≤ FFh 0≤b≤7 [f] ← 1 None Bit b in [f] is set to 1.
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FS98O22 CALL Syntax Operation Flag Affected Description Cycle Clear f CLRF f 0 ≤ f ≤ 255 [f] ← 0 None Reset the content of memory address f 1 Before instruction: WORK = 5Ah After instruction: WORK = 00h FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y CLRF Syntax Subroutine CALL CALL k 0 ≤ k ≤ 1FFFh Push Stack [Top Stack] ← PC + 1 PC ← k None Subroutine Call. First, return address PC + 1 is pushed onto the stack. The immediate address is loaded into PC.
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FS98O22 DECF Syntax Operation Flag Affected Description FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y Cycle Example 1: DECF OPERAND,0 Decrement f DECF f, d 0 ≤ f ≤ 255 d ∈ [0,1] [Destination] ← [f] -1 Z [f] is decremented. If d is 0, the result is stored in the W register. If d is 1, the result is stored back in [f].
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FS98O22 INCF Syntax Operation Flag Affected Description FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y Cycle Example 1: INCF OPERAND,0 Increment f INCF f, d 0 ≤ f ≤ FFh d ∈ [0,1] [Destination] ← [f] +1 Z [f] is incremented. If d is 0, the result is stored in the W register. If d is 1, the result is stored back in [f].
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FS98O22 Inclusive OR W with f IORWF f, d 0 ≤ f ≤ FFh d ∈ [0,1] Operation [Destination] ← [W] | [f] Flag Affected Z Description Inclusive OR the content of the W register and [f]. If d is 0, the result is stored in the W register. If d is 1, the result is stored back in [f].
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FS98O22 RETFIE Syntax Operation Flag Affected Description Cycle Return and move literal to W RETLW k 0 ≤ k ≤ FFh [W] ← k [Top Stack] => PC Pop Stack None Move the eight-bit literal “k” to the content of the W register. The program counter is loaded from the top stack, then pop stack. 2 FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y RETLW Syntax Return from Interrupt RETFIE [Top Stack] => PC Pop Stack 1 => GIE None The program counter is loaded from the top stack, then pop stack.
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FS98O22 RRF Syntax Operation FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y Flag Affected Description Rotate right [f] through Carry RRF f, d 0 ≤ f ≤ FFh d ∈ [0,1] [Destination] ← [f] [Destination<7>] ← C C ← [f<7>] C [f] is rotated one bit to the right through the Carry bit. If d is 0, the result is stored in the W register. If d is 1, the result is stored back in [f].
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FS98O22 Subtract W from f SUBWF f, d 0 ≤ f ≤ FFh d ∈ [0,1] Operation [Destination] ← [f] – [W] Flag Affected C, DC, Z Description Subtract the content of the W register from [f]. If d is 0, the result is stored in the W register.
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FS98O22 XORLW Syntax Operation Flag Affected Description 5Fh 1 Before instruction: W = Ach After instruction: W = F3h FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y Cycle Example: XORLW Exclusive OR literal with W XORLW k 0 ≤ k ≤ FFh [W] ← [W] XOR k Z Exclusive OR the content of the W register and the eight-bit literal “k”. The result is stored in the W register.
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FS98O22 15. Package Information FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y 15.1. Package Outline Figure 15-1 FS98O22 package outline Rev. 1.
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FS98O22 FO Fo P R r R ro TU ef pe NE er rti ' en es ce O nl y 15.2. Package Outline(3.2mm QFP100) Figure 15-2 FS98O22 3.2mm QFP100 package outline 16. Revision History Ver. 1.0 1.1 Date 2006/02/16 2006/03/29 1.2 1.3 2008/12/25 2009/07/08 Page All 17~19 23 134~135 33 20 1.4 1.5 1.6 2011/07/21 2014/01/14 2014/05/22 20 20 20 2 Rev. 1.6 Description Initial release.