Specifications

8 JN-DS-JN5148-001 1v9 © NXP Laboratories UK 2013
1.4 Block Diagram
32-bit RISC CPU
Reset
SPI
Master
MUX
UART0
UART1
Wakeup
Timer1
Wakeup
Timer0
Security
Coprocessor
DIO6/TXD0/JTAG_TDO
DIO7/RXD0/JTAG_TDI
DIO4/CTS0/JTAG_T CK
DIO5/RTS0/JTAG_T MS
DIO19/TXD1/JTAG_TDO
DIO17/CTS1/IP_SEL/DAI_SCK/
J T A G_T CK
DIO18/RTS1/IP_INT/DAI_SDOUT/
J TA G_T MS
Digital
Baseband
Radio
Programmable
Interrupt
Controller
Timer0
2-wire
Interf ace
Timer1
SPICLK
DIO10/TIM0OUT/32KXTALOUT
SPIMOSI
SPIMISO
SPISEL0
DIO0/SPISEL1
DIO3/SPISEL4/RFTX
DIO2/SPISEL3/RFRX
DIO1/SPISEL2/PC0
DIO9/TIM0CAP/32KXTALIN/32KIN
DIO8/TIM0CK_GT/PC1
DIO13/TIM1OUT/ADE/DAI_SDIN
DIO11/TIM1CK_GT/TIM2OUT
DIO12/TIM1CAP/ADO/DAI_WS
DIO14/SIF_CLK/IP_CLK
DIO15/SIF_D/IP_DO
DIO16/RXD1/IP_DI/JTAG_TDI
From Peripherals
RE SET N
Wireless
Transceiv er
32MHz Clock
Generator
XT A L_ IN
XT A L_ OUT
RF_IN
VCOTUNE
Tick Timer
Voltage
Regulators
1.8V
VDD1
VDD2
Intelligent
Peripheral
IBAIS
VB_XX
Clock Divider
Multiplier
Timer2
SPISEL1
SPISEL2
SPISEL3
SPISEL4
TXD0
RXD0
RTS0
CTS0
TXD1
RXD1
RTS1
CTS1
TIM0CK_GT
TIM 0 CA P
TIM0OUT
TIM1CK_GT
TIM 1 CA P
TIM1OUT
TIM2OUT
SIF_D
S IF_CLK
IP_DO
I P _DI
IP _ INT
IP_CLK
IP_SEL
4-wire
Digital
Audio
Interf ace
I2S_OUT
I2S_DIN
I2S_CLK
I2S_SYNC
Pulse
Counters
PC0
PC1
JTAG
Debug
JTAG_TDI
JTAG_TMS
JTAG_TCK
JTAG_TDO
RAM
128kB
ROM
128kB
OTP
eFuse
32kHz
RC
Osc
32kHz Clock
Select
32KIN
32kHz
Cl oc k
Gen
32KXTALIN
32KXTALOUT
Antenna
Div ersity
ADO
ADE
T i me
Of
Flight
Sample
FIFO
DIO20/RXD1/JTAG_TDI
24MHz
RC Osc
Comparator2
COMP 2 P
COMP 2 M
Comparator1
COMP1P/
EXT _PA_ C
COMP 1 M/
EXT _PA_ B
DAC1
DAC2
DAC1
DAC2
ADC
M
U
X
ADC4
ADC1
ADC2
ADC3
Temperature
Sensor
Supply Monitor
CPU and 16MHz
System Clock
Watchdog
Timer
Brown-out
Detect
Figure 1: JN5148 Block Diagram
DIO 16/IP_DI