Specifications

68 JN-DS-JN5148-001 1v9 © NXP Laboratories UK 2013
22.3.2 SPI MasterTiming
t
SSH
t
SSS
t
CK
t
SI
t
HI
MOSI
(mode=1,3)
SS
MOSI
(mode=0,2)
MISO
(mode=0,2)
MISO
(mode=1,3)
t
VO
t
VO
CLK
(mode=0,1)
t
SI
t
HI
CLK
(mode=2,3)
Figure 48: SPI Timing (Master)
Parameter Symbol Min Max Unit
Clock period
t
CK
62.5
-
ns
Data setup time t
SI
16.7 @ 3.3V
18.2 @ 2.7V
21.0 @ 2.0V
- ns
Data hold time
t
HI
0
ns
Data invalid period t
VO
- 15 ns
Select set-up period t
SSS
60 - ns
Select hold period t
SSH
30 (SPICLK = 16MHz)
0 (SPICLK<16MHz, mode=0 or 2)
60 (SPICLK<16MHz, mode=1 or 3)
- ns
22.3.3 Intelligent Peripheral (SPI Slave) Timing
IP_SEL
IP_CLK
IP_DI
IP_DO
t
si
t
hi
t
vo
t
sss
t
ssh
t
ck
t
lz
t
hz
Figure 49: Intelligent Peripheral (SPI Slave) Timing