Specifications

34 JN-DS-JN5148-001 1v9 © NXP Laboratories UK 2013
4-wire
Digital Audio
Interface
Antenna
Diversity
JTAG
Debug
Pulse
Counters
Intelligent
Peripheral
MUX
2-wire
Interface
Timer2
Timer1
Timer0
UART1
UART0
SPI
Master
SPISEL1
SPISEL2
SPISEL3
SPISEL4
TXD0
RXD0
RTS0
CTS0
TXD1
RXD1
RTS1
CTS1
TIM0CK_GT
TIM0OUT
TIM0CAP
TIM1CK_GT
TIM1OUT
TIM1CAP
TIM2OUT
SIF_D
SIF_CLK
IP_DO
IP_DI
IP_INT
IP_CLK
IP_SEL
PC0
PC1
JTAG_TDI
JTAG_TMS
JTAG_TCK
JTAG_TDO
ADO
ADE
I2S_OUT
I2S_DIN
I2S_CLK
I2S_SYNC
SPICLK
SPIMOSI
SPIMISO
SPISEL0
DIO0/SPISEL1
DIO1/SPISEL2/PC0
DIO2/SPISEL3/RFRX
DIO3/SPISEL4/RFTX
DIO4/CTS0/JTAG_TCK
DIO5/RTS0/JTAG_TMS
DIO6/TXD0/JTAG_TDO
DIO7/RXD0/JTAG_TDI
DIO8/TIM0CK_GT/PC1
DIO9/TIM0CAP/32KXTALIN/32KIN
DIO10/TIM0OUT/32KXTALOUT
DIO11/TIM1CK_GT/TIM2OUT
DIO12/TIM1CAP/ADO/DAI_WS
DIO13/TIM1OUT/ADE/DAI_SDN
DIO14/SIF_CLK/IP_CLK
DIO15/SIF_D/IP_DO
DIO16/IP_DI
DIO17/CTS1/IP_SEL/DAI_SCK/
JTAG_TCK
DIO18/RTS1/IP_INT/DAI_SDOUT/
JTAG_TMS
DIO19/TXD1/JTAG_TDO
DIO20/RXD1/JTAG_TDI
Figure 22 DIO Block Diagram