Specifications

14 JN-DS-JN5148-001 1v9 © NXP Laboratories UK 2013
I
O
IE
VDD2
VSS
Pu
R
PU
R
PROT
OE
DIO[x] Pin
Figure 4: DIO Pin Equivalent Schematic
In reset, the digital peripherals are all off and the DIO pins are set as high-impedance inputs. During sleep and deep
sleep, the DIO pins retain both their input/output state and output level that was set as sleep commences. If the DIO
pins were enabled as inputs and the interrupts were enabled then these pins may be used to wake up the JN5148
from sleep.