Specifications

© 2008 Microchip Technology Inc. DS80258G-page 9
dsPIC30F6010A/6015
9. Module: I
2
C
When the I
2
C module is configured as a slave,
either in single-master or multi-master mode, the
I
2
C receiver buffer is filled whether a valid slave
address is detected or not. Therefore, an I
2
C
receiver overflow condition occurs and this condi-
tion is indicated by the I2COV flag in the I2CSTAT
register.
This overflow condition inhibits the ability to set the
I
2
C receive interrupt flag (SI2CF) when the last
valid data byte is received. Therefore, the I
2
C
slave Interrupt Service Routine (ISR) is not called
and the I
2
C receiver buffer is not read prior
receiving the next data byte.
Work around
s
To avoid this issue, either of the following two work
arounds can be implemented, depending on the
application requirements.
Work around 1:
For applications in which the I
2
C receiver interrupt
is not required, the following procedure can be
used to receive valid data bytes:
1. Wait until the RBF flag is set.
2. Poll the I
2
C receiver interrupt SI2CIF flag.
3. If SI2CF is not set in the corresponding
Interrupt Flag Status (IFSx) register, a valid
address or data byte has not been received for
the current slave. Execute a dummy read of
the I
2
C receiver buffer, I2CRCV; this will clear
the RBF flag. Go back to step 1 until SI2CF is
set and then continue to Step 4.
4. If the SI2CF is set in the corresponding
Interrupt Flag Status (IFSx) register, valid data
has been received. Check the D_A flag to
verify that an address or a data byte has been
received.
5. Read the I2CRCV buffer to recover valid data
bytes. This will also clear the RBF flag.
6. Clear the I
2
C receiver interrupt flag SI2CF.
7. Go back to step 1 to continue receiving
incoming data bytes.
Work around 2:
Use this work around for applications in which the
I
2
C receiver interrupt is required. Assuming that
the RBF and the I2COV flags in the I2CSTAT
register are set due to previous data transfers in
the I
2
C bus (i.e., between master and other
slaves); the following procedure can be used to
receive valid data bytes:
1. When a valid slave address byte is detected,
SI2CF bit is set and the I
2
C slave interrupt
service routine is called; however, the RBF and
I2COV bits are already set due to data
transfers between other I
2
C nodes.
2. Check the status of the D_A flag and the
I2COV flag in the I2CSTAT register when
executing the I
2
C slave service routine.
3. If the D_A flag is cleared and the I2COV flag
are set, an invalid data byte was received but a
valid address byte was received. The overflow
condition occurred because the I
2
C receive
buffer was overflowing with previous I
2
C data
transfers between other I
2
C nodes. This
condition only occurs after a valid slave
address was detected.
4. Clear the I2COV flag and perform a dummy
read of the I
2
C receiver buffer, I2CRCV, to
clear the RBF bit and recover the valid address
byte. This action will also avoid the loss of the
next data byte due to an overflow condition.
5. Verify that the recovered address byte
matches the current slave address byte. If they
match, the next data to be received is a valid
data byte.
6. If the D_A flag and the I2COV flag are both set,
a valid data byte was received and a previous
valid data byte was lost. It will be necessary to
code for handling this overflow condition.
10. Module: Motor Control PWM – PWM
Counter Register
If the PTDIR bit is set (when PTMR is counting
down), and the CPU execution is halted (after a
breakpoint is reached), PTMR will start counting
up as if PTDIR was zero.
Work around
None.