Specifications

dsPIC30F6010A/6015

4. Module: Quadrature Encoder Interface

The Index Pulse Reset mode of the QEI does not

work properly when used along with count error

detection. When counting upwards, the POSCNT

index pulse is received. The extra count will

generate a false count error interrupt.

Work around

There are multiple work arounds for this issue,

depending on the specific requirements of the

application:

1. Ignore count error interrupts when the counting

direction is upwards and the POSCNT register

has the value of MAXCNT + 1.

2. The user may disable count error interrupts by

setting the CEID bit in the DFLTCON register.

3. The user may disable the index pulse reset

feature by clearing the POSRES bit

(QEICON<2>). Writing QEICON = 0x0600 will

provide a QEI interrupt each time an index

pulse is received, but the POSCNT register will

not be modified. The POSCNT register value

can be read in the QEI interrupt handler and

used as an offset value to calculate the

absolute position of the encoder disc with

respect to the index pulse.

5. Module: INT0, ADC and Sleep Mode

ADC event triggers from the INT0 pin will not

wake-up the device from Sleep mode if the SMPI

bits are non-zero. This means that if the ADC is

configured to generate an interrupt after a certain

number of INT0 triggered conversions, the ADC

conversions will not be triggered and the device

will remain in Sleep. The ADC will perform

conversions and wake-up the device only if it is

configured to generate an interrupt after each INT0

triggered conversion (SMPI<3:0> = 0000).

Work around

None. If ADC event trigger from the INT0 pin is

required, initialize SMPI<3:0> to ‘0000’ (interrupt

on every conversion).