Specifications

© 2008 Microchip Technology Inc. DS80258G-page 11
dsPIC30F6010A/6015
18. Module: I
2
C
When the I
2
C module is enabled by setting the
I2CEN bit in the I2CCON register, the dsPIC DSC
device generates a glitch on the SDA and SCL
pins. This glitch falsely indicates “Communication
Start” to all devices on the I
2
C bus, and can cause
a bus collision in a multi-master configuration.
Additionally, when the I2CEN bit is set, the S and
P bits of the I
2
C module are set to values ‘1’ and
‘0’, respectively, which indicate a “Communication
Start” condition.
Work around
s
To avoid this issue, either of the following two work
arounds can be implemented, depending on the
application requirements.
Work around 1:
In a single-master environment, add a delay
between enabling the I
2
C module and the first data
transmission. The delay should be equal to or
greater than the time it takes to transmit two data
bits.
In the multi-master configuration, in addition to the
delay, all other I
2
C masters should be synchro-
nized and wait for the I
2
C module to be initialized
before initiating any kind of communication.
Work around 2:
In dsPIC DSC devices in which the I
2
C module is
multiplexed with other modules that have
precedence in the use of the pin, it is possible to
avoid this glitch by enabling the higher priority
module before enabling the I
2
C module.
Use the following procedure to implement this
work around:
1. Enable the higher priority peripheral module
that is multiplexed on the same pins as the I
2
C
module.
2. Set up and enable the I
2
C module.
3. Disable the higher priority peripheral module
that was enabled in step 1.
Note: Work around 2 works only for devices that
share the SDA and SCL pins with another
peripheral that has a higher precedence
over the port latch, such as the UART. The
priority is shown in the pin diagram located
in the data sheet. For example, if the SDA
and SCL pins are shared with the UART
and SPI pins, and the UART has higher
precedence on the port latch pin.