User Manual

ADCP-75-192 • Issue D • October 2005 • Section 6: Software Updates
Page 6-4
 2005, ADC Telecommunications, Inc.
When evaluating the process list, it is important to be sure that the process IDs of each of the
listed processes above stay stable to ensure that processes are not continually restarting. Run
the command ps ax | grep /usr/bin/ multiple times over the course of a minute or two to be
sure that this is the case.
In addition to the above processes, it must be verified that the SNMP agent software is
running. This is done by entering: ps as | grep "/usr/local/sbin" and verifying that
/usr/local/sbin/snmpd is one of the processes listed.
Evaluate the software version to be sure that it matches what is intended. This can be done
from the NMS by evaluating the Network Node MIB field
transceptNetworkNodeOpencellSoftwareRev. Alternatively, this value can be retrieved in the
telnet session to the CPU opened in the previous step by entering:
snmpget localhost patriots transceptNetworkNodeOpencellSoftwareRev.0
On the upgraded CPU, verify pathtrace values are as expected by viewing the
transceptOpencellPathtraceTable MIB. Refer to the above "Preliminary Steps" section for
details.
On the upgraded RAN CPU, verify PAs are functioning and power levels are as expected.
Refer to the above "Preliminary Steps" section for details.
3.4 Failed Upgrades
In the case of a failed upgrade, it will be desirable to attempt to return the target CPU to its
previous revision by uninstalling the most recent software upgrade. This action will be
accomplished with the use of a downgrade script that is installed as part of the upgrade. The
name of the downgrade script will contain the name of the version being downgraded to; for
example, hr-2.0.0-downgrade would be used to revert a CPU that has been upgraded to
version 2.1.0 back to 2.0.0.
It is important that, upon completion of a downgrade, the verification steps described in the
previous section are taken to ensure that the CPU is left in an operational state.
3.5 FPGA Updates
Certain software releases will contain updates to the FPGA images that the Digivance CXD
modules load on startup. These FPGA image updates need to be programmed into an
EEPROM on the module(s) in question. This is an operator initiated event which is described
in detail below. Depending on the module(s) being updated with new FPGA images, this
action could take as long as 20-30 minutes to complete
Note: When the FGPA’s download is completed, service will be briefly interrupted during
board reset.