Product guide

19
Note
Chapter Two System Features
Processor
Each Pentium II or Pentium III processor is packaged in a cartridge. The cartridge
includes the processor core with an integrated 16 KB primary (L1) cache, the
secondary (L2) cache, and a back cover.
The processor implements the MMX
™
technology and maintains full backward
compatibility with the 8086, 80286, Intel386
TM
, Intel486
TM
, Pentium, Pentium Pro and
previous Pentium II processors. The processor’s numeric coprocessor significantly
increases the speed of floating point operations and complies with ANSI/IEEE
standard 754-1985.
Each processor cartridge connects to the server board through a 242-pin edge
connector. The cartridge is secured by a retention mechanism attached to the
server board. Depending on configuration, your server may have one or two
processors.
The processor external interface is MP (Multi-Processor) ready and operates at
100 MHz. The processor contains a local APIC (Advanced Programmable Interrupt
Controller) section for interrupt handling in MP and UP (Uni-Processor)
environments.
The second level cache is located on the substrate of the S.E.C. cartridge. The
cache includes burst pipelined synchronous static RAM (BSRAM). The L2 cache is
offered in 512 KB configurations only, with error correcting code (ECC) that operates
at half the core clock rate.
If you install a processor that is 550 MHz, and you use the server management
feature board, you must run the FRU / SDR update utility.
System Memory
Only 100 MHz PC/100 ECC or Non-ECC SDRAM is supported by the server board.
Memory is partitioned as four banks of SDRAM DIMMs, each providing 72-bits of
noninterleaved memory (64-bit main memory plus ECC):
q Install from 64 MB to 2 GB of memory, using registered DIMMs.
q Install from 32 MB to 2 GB of memory, using unbuffered DIMMs.
Memory should be added in order from slot 1 to slot 4.
Do not mix registered and unbuffered memory. Non-ECC memory may be installed
but ECC memory is recommended in a server environment. Mixing Non-ECC
memory and ECC memory causes all ECC features to be disabled.
Note
The controller automatically detects, sizes, and initializes the memory array
depending on the type, size and speed of the installed DIMMs. It reports memory
size and allocation to the server via configuration registers.