Technical data
termiox(7I) Ioctl Requests SunOS 5.5
If CTSXON is set, output will occur only if the Clear To Send (CTS) circuit (line) is raised
by the connected device. If the CTS line is lowered by the connected device, output is
suspended untilCTS is raised.
If DTRXOFF is set, theDTE Ready (DTR) circuit (line) will be raised, and if the asynchro-
nous port needs to have its input stopped, it will lower the DTE Ready (DTR) line. If the
DTR line is lowered, it is assumed that the connected device will stop its output untilDTR
is raised.
If CDXON is set, output will occur only if the Received Line SignalDetector (CD) circuit
(line) is raised by the connected device. If the CD line is lowered by the connected device,
output is suspended untilCD is raised.
If ISXOFF is set, and if the isochronous port needs to have its input stopped, it will stop
the outgoing clock signal. It is assumed that the connected device is using this clock sig-
nal to create its output. Transit and receive clock sources are programmed using the
x_cflag fields. If the port is not programmed for external clock generation, ISXOFF is
ignored. Output isochronous flow control is supported by appropriate clock source pro-
gramming using the x_cflag field and enabled at the remote connected device.
The x_cflag field specifies the system treatment of clock modes.
XMTCLK 0000007 Transmit clock source:
XCIBRG 0000000 Get transmit clock from internal baud rate
generator.
XCTSET 0000001 Get transmit clock from transmitter signal
element timing (DCE source) lead, CCITT
V.24 circuit 114, EIA-232-D pin 15.
XCRSET 0000002 Get transmit clock from receiver signal
element timing (DCE source) lead, CCITT
V.24 circuit 115, EIA-232-D pin 17.
RCVCLK 0000070 Receive clock source:
RCIBRG 0000000 Get receive clock from internal baud rate
generator.
RCTSET 0000010 Get receive clock from transmitter signal
element timing (DCE source) lead, CCITT
V.24 circuit 114, EIA-232-D pin 15.
RCRSET 0000020 Get receive clock from receiver signal
element timing (DCE source) lead, CCITT
V.24 circuit 115, EIA-232-D pin 17.
TSETCLK 0000700 Transmitter signal elementtiming (DTE source)
lead, CCITT V.24 circuit 113, EIA-232-D
pin 24, clock source:
TSETCOFF 0000000 TSET clock not provided.
TSETCRBRG 0000100 Output receive baud rate generator on
circuit 113.
7I-366 modified 3 Jul 1990